diff options
| author | SeungRyeol Lee <zizztux@gmail.com> | 2018-07-24 05:14:05 +0900 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2018-07-23 13:14:05 -0700 |
| commit | 2cd60b277e909a5599ca48e4561cbfbc61460186 (patch) | |
| tree | 9b5ed9cb234ee1de118bf6bad1eb584b5905f5b7 | |
| parent | 95487c248a6eb660b9bd1aa49e28da5a1ab21059 (diff) | |
| download | riscv-isa-sim-2cd60b277e909a5599ca48e4561cbfbc61460186.zip riscv-isa-sim-2cd60b277e909a5599ca48e4561cbfbc61460186.tar.gz riscv-isa-sim-2cd60b277e909a5599ca48e4561cbfbc61460186.tar.bz2 | |
Fix using the uninitialized disassemble object. (#220)
This fixes runtime crash when custom extension registers its
disassembly.
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 9fc5d5f..52f69c1 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -24,11 +24,11 @@ processor_t::processor_t(const char* isa, simif_t* sim, uint32_t id, : debug(false), halt_request(false), sim(sim), ext(NULL), id(id), halt_on_reset(halt_on_reset), last_pc(1), executions(1) { + disassembler = new disassembler_t(max_xlen); parse_isa_string(isa); register_base_instructions(); mmu = new mmu_t(sim, this); - disassembler = new disassembler_t(max_xlen); reset(); } |