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| author | Andrew Waterman <andrew@sifive.com> | 2023-01-11 09:47:11 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-01-11 09:47:11 -0800 |
| commit | 9874c1767179250e25094ccc6757a5faad9d99d1 (patch) | |
| tree | 00e8d8bfbe4e1383e066f215d0d1649bd16ec5a1 | |
| parent | 3b2e8d53b39b8baba8d2e4c31408d92776b32e86 (diff) | |
| parent | ecda7372d7925c378628652f64c6a887fe371be2 (diff) | |
| download | riscv-isa-sim-9874c1767179250e25094ccc6757a5faad9d99d1.zip riscv-isa-sim-9874c1767179250e25094ccc6757a5faad9d99d1.tar.gz riscv-isa-sim-9874c1767179250e25094ccc6757a5faad9d99d1.tar.bz2 | |
Merge pull request #1223 from riscv-software-src/readme
Fix supported debug version, use extension names
| -rw-r--r-- | README.md | 3 |
1 files changed, 2 insertions, 1 deletions
@@ -37,7 +37,8 @@ Spike supports the following RISC-V ISA features: - Svnapot extension, v1.0 - Svpbmt extension, v1.0 - Svinval extension, v1.0 - - Debug v0.14 + - Sdext extension, v1.0-STABLE + - Sdtrig extension, v1.0-STABLE - 4 triggers support type=2 (mcontrol), type=4 (itrigger), type=5 (etrigger), type=6 (mcontrol6), and type=15 (disabled) - Smepmp extension v1.0 - Smstateen extension, v1.0 |