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| author | Andrew Waterman <andrew@sifive.com> | 2023-01-03 22:22:36 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-01-05 00:20:28 -0600 |
| commit | 571945ca6e55191866aefe62ec4d9d17145cc174 (patch) | |
| tree | 6e43b6860f983be0fe6bdd053458d2fdefe0e0bf | |
| parent | 3d63b06faee13536710fc7db08979797182684fb (diff) | |
| download | riscv-isa-sim-571945ca6e55191866aefe62ec4d9d17145cc174.zip riscv-isa-sim-571945ca6e55191866aefe62ec4d9d17145cc174.tar.gz riscv-isa-sim-571945ca6e55191866aefe62ec4d9d17145cc174.tar.bz2 | |
Remove vestigial UNUSED annotation
It dates back to when this code was ifdef'd.
| -rw-r--r-- | riscv/execute.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index 844f2b8..b093e72 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -150,7 +150,7 @@ static void commit_log_print_insn(processor_t *p, reg_t pc, insn_t insn) fprintf(log_file, "\n"); } -inline void processor_t::update_histogram(reg_t UNUSED pc) +inline void processor_t::update_histogram(reg_t pc) { if (histogram_enabled) pc_histogram[pc]++; |