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author | Andrew Waterman <andrew@sifive.com> | 2023-01-11 16:56:18 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2023-01-11 22:01:24 -0800 |
commit | 4efafebef052693fef045ab918c2681396af3c9f (patch) | |
tree | 379e033c1f1e1e06032ea084407c1762ecca71d4 | |
parent | 2cb5cf5d66d5df8f310a335032d836ad5f0dc977 (diff) | |
download | riscv-isa-sim-4efafebef052693fef045ab918c2681396af3c9f.zip riscv-isa-sim-4efafebef052693fef045ab918c2681396af3c9f.tar.gz riscv-isa-sim-4efafebef052693fef045ab918c2681396af3c9f.tar.bz2 |
-rw-r--r-- | riscv/execute.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index b093e72..76f0322 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -281,7 +281,7 @@ void processor_t::step(size_t n) for (auto ic_entry = _mmu->access_icache(pc); ; ) { auto fetch = ic_entry->data; pc = execute_insn_fast(this, pc, fetch); - ic_entry = ic_entry->next; + ic_entry = &_mmu->icache[_mmu->icache_index(pc)]; if (unlikely(ic_entry->tag != pc)) break; if (unlikely(instret + 1 == n)) |