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author | Andrew Waterman <andrew@sifive.com> | 2023-01-03 16:43:31 -0800 |
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committer | GitHub <noreply@github.com> | 2023-01-03 16:43:31 -0800 |
commit | 2a95b4e198ed6a3933b55cc86f590dd5d3355b5c (patch) | |
tree | f8b1a845c947cf073c41852a7c2eefff4b5fb2ec | |
parent | 07647a9b53f482bb299ab783090af53995b4817e (diff) | |
parent | 96be756b53c46e297fe8a2af916060013860f1bb (diff) | |
download | riscv-isa-sim-2a95b4e198ed6a3933b55cc86f590dd5d3355b5c.zip riscv-isa-sim-2a95b4e198ed6a3933b55cc86f590dd5d3355b5c.tar.gz riscv-isa-sim-2a95b4e198ed6a3933b55cc86f590dd5d3355b5c.tar.bz2 |
Merge pull request #1203 from riscv-software-src/misa-c-read-only
Make misa.C read-only
-rw-r--r-- | riscv/csrs.cc | 7 | ||||
-rw-r--r-- | riscv/processor.h | 3 |
2 files changed, 3 insertions, 7 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index d7d0a86..de9381c 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -601,13 +601,12 @@ bool sstatus_csr_t::enabled(const reg_t which) { misa_csr_t::misa_csr_t(processor_t* const proc, const reg_t addr, const reg_t max_isa): basic_csr_t(proc, addr, max_isa), max_isa(max_isa), - write_mask(max_isa & (0 // allow MAFDQCHV bits in MISA to be modified + write_mask(max_isa & (0 // allow MAFDQHV bits in MISA to be modified | (1L << ('M' - 'A')) | (1L << ('A' - 'A')) | (1L << ('F' - 'A')) | (1L << ('D' - 'A')) | (1L << ('Q' - 'A')) - | (1L << ('C' - 'A')) | (1L << ('H' - 'A')) | (1L << ('V' - 'A')) ) @@ -619,10 +618,6 @@ reg_t misa_csr_t::dependency(const reg_t val, const char feature, const char dep } bool misa_csr_t::unlogged_write(const reg_t val) noexcept { - // the write is ignored if increasing IALIGN would misalign the PC - if (!(val & (1L << ('C' - 'A'))) && (state->pc & 2)) - return false; - reg_t adjusted_val = val; adjusted_val = dependency(adjusted_val, 'D', 'F'); adjusted_val = dependency(adjusted_val, 'Q', 'D'); diff --git a/riscv/processor.h b/riscv/processor.h index f65faf6..86d89fb 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -236,7 +236,8 @@ public: return impl_table[impl]; } reg_t pc_alignment_mask() { - return ~(reg_t)(extension_enabled(EXT_ZCA) ? 0 : 2); + const int ialign = extension_enabled(EXT_ZCA) ? 16 : 32; + return ~(reg_t)(ialign == 16 ? 0 : 2); } void check_pc_alignment(reg_t pc) { if (unlikely(pc & ~pc_alignment_mask())) |