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| author | Parshintsev Anatoly <anatoly.parshintsev@syntacore.com> | 2023-01-09 19:18:50 +0300 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-01-10 15:44:10 -0800 |
| commit | 28eb7aa8bece565adac4245815c80ba3fc65fc8a (patch) | |
| tree | cf1b92325453869b90314d9a293006a3bafae577 | |
| parent | f403cb9e542155787b862d726ba334e0d0895c74 (diff) | |
| download | riscv-isa-sim-28eb7aa8bece565adac4245815c80ba3fc65fc8a.zip riscv-isa-sim-28eb7aa8bece565adac4245815c80ba3fc65fc8a.tar.gz riscv-isa-sim-28eb7aa8bece565adac4245815c80ba3fc65fc8a.tar.bz2 | |
change mem_cfg_t to accept cases when (base + size) is at 64-bit address space border
| -rw-r--r-- | riscv/cfg.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/riscv/cfg.cc b/riscv/cfg.cc index ef1d579..457aa92 100644 --- a/riscv/cfg.cc +++ b/riscv/cfg.cc @@ -17,7 +17,11 @@ bool mem_cfg_t::check_if_supported(reg_t base, reg_t size) // ask that the page size is a multiple of the minimum page size, that the // page is aligned to the minimum page size, that the page is non-empty and // that the top address is still representable in a reg_t. + // + // Note: (base + size == 0) part of the assertion is to handle cases like + // { base = 0xffff_ffff_ffff_f000, size: 0x1000 } return (size % PGSIZE == 0) && (base % PGSIZE == 0) && - (base + size > base); + (size > 0) && + ((base + size > base) || (base + size == 0)); } |