Add logged variants of insn templates

6 files changed, 36 insertions, 18 deletions

diff --git a/riscv/insn_template.cc b/riscv/insn_template.cc
index e6a2f52..9fc6e7e 100644
--- a/riscv/insn_template.cc
+++ b/riscv/insn_template.cc
@@ -1,9 +1,9 @@
 // See LICENSE for license details.
 
-#include "insn_template.h"
+#include "insn_template_TYPE.h"
 #include "insn_macros.h"
 
-reg_t rv32i_NAME(processor_t* p, insn_t insn, reg_t pc)
+reg_t TYPE_rv32i_NAME(processor_t* p, insn_t insn, reg_t pc)
 {
   #define xlen 32
   reg_t npc = sext_xlen(pc + insn_length(OPCODE));
@@ -13,7 +13,7 @@ reg_t rv32i_NAME(processor_t* p, insn_t insn, reg_t pc)
   return npc;
 }
 
-reg_t rv64i_NAME(processor_t* p, insn_t insn, reg_t pc)
+reg_t TYPE_rv64i_NAME(processor_t* p, insn_t insn, reg_t pc)
 {
   #define xlen 64
   reg_t npc = sext_xlen(pc + insn_length(OPCODE));
@@ -26,7 +26,7 @@ reg_t rv64i_NAME(processor_t* p, insn_t insn, reg_t pc)
 #undef CHECK_REG
 #define CHECK_REG(reg) require((reg) < 16)
 
-reg_t rv32e_NAME(processor_t* p, insn_t insn, reg_t pc)
+reg_t TYPE_rv32e_NAME(processor_t* p, insn_t insn, reg_t pc)
 {
   #define xlen 32
   reg_t npc = sext_xlen(pc + insn_length(OPCODE));
@@ -36,7 +36,7 @@ reg_t rv32e_NAME(processor_t* p, insn_t insn, reg_t pc)
   return npc;
 }
 
-reg_t rv64e_NAME(processor_t* p, insn_t insn, reg_t pc)
+reg_t TYPE_rv64e_NAME(processor_t* p, insn_t insn, reg_t pc)
 {
   #define xlen 64
   reg_t npc = sext_xlen(pc + insn_length(OPCODE));
diff --git a/riscv/insn_template_fast.h b/riscv/insn_template_fast.h
new file mode 100644
index 0000000..7673c17
--- /dev/null
+++ b/riscv/insn_template_fast.h
@@ -0,0 +1,4 @@
+// See LICENSE for license details.
+
+#define DECODE_MACRO_USAGE_FAST
+#include "insn_template.h"
diff --git a/riscv/insn_template_logged.h b/riscv/insn_template_logged.h
new file mode 100644
index 0000000..1b4d65f
--- /dev/null
+++ b/riscv/insn_template_logged.h
@@ -0,0 +1,4 @@
+// See LICENSE for license details
+
+#define DECODE_MACRO_USAGE_LOGGED
+#include "insn_template.h"
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 2e6d0d2..ddb1823 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -1054,18 +1054,18 @@ void processor_t::register_base_instructions()
   #undef DECLARE_OVERLAP_INSN
 
   #define DEFINE_INSN(name) \
-    extern reg_t rv32i_##name(processor_t*, insn_t, reg_t); \
-    extern reg_t rv64i_##name(processor_t*, insn_t, reg_t); \
-    extern reg_t rv32e_##name(processor_t*, insn_t, reg_t); \
-    extern reg_t rv64e_##name(processor_t*, insn_t, reg_t); \
+    extern reg_t fast_rv32i_##name(processor_t*, insn_t, reg_t); \
+    extern reg_t fast_rv64i_##name(processor_t*, insn_t, reg_t); \
+    extern reg_t fast_rv32e_##name(processor_t*, insn_t, reg_t); \
+    extern reg_t fast_rv64e_##name(processor_t*, insn_t, reg_t); \
     if (name##_supported) { \
       register_insn((insn_desc_t) { \
         name##_match, \
         name##_mask, \
-        rv32i_##name, \
-        rv64i_##name, \
-        rv32e_##name, \
-        rv64e_##name}); \
+        fast_rv32i_##name, \
+        fast_rv64i_##name, \
+        fast_rv32e_##name, \
+        fast_rv64e_##name}); \
     }
   #include "insn_list.h"
   #undef DEFINE_INSN
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 202c717..4a3470f 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -38,6 +38,8 @@ riscv_hdrs = \
 	extension.h \
 	rocc.h \
 	insn_template.h \
+	insn_template_fast.h \
+	insn_template_logged.h \
 	debug_module.h \
 	debug_rom_defines.h \
 	remote_bitbang.h \
@@ -74,7 +76,8 @@ riscv_install_hdrs = \
 	vector_unit.h \
 
 riscv_precompiled_hdrs = \
-	insn_template.h \
+	insn_template_fast.h \
+	insn_template_logged.h \
 
 riscv_srcs = \
 	isa_parser.cc \
@@ -1358,8 +1361,10 @@ riscv_insn_list = \
 	$(riscv_insn_svinval) \
 	$(riscv_insn_ext_cmo) \
 
-riscv_gen_srcs = \
-	$(addsuffix .cc,$(riscv_insn_list))
+riscv_fast_gen_srcs = $(addsuffix _fast.cc,$(riscv_insn_list))
+riscv_logged_gen_srcs = $(addsuffix _logged.cc,$(riscv_insn_list))
+
+riscv_gen_srcs = $(riscv_fast_gen_srcs) $(riscv_logged_gen_srcs)
 
 insn_list.h: $(src_dir)/riscv/riscv.mk.in
 	for insn in $(foreach insn,$(riscv_insn_list),$(subst .,_,$(insn))) ; do \
@@ -1367,8 +1372,11 @@ insn_list.h: $(src_dir)/riscv/riscv.mk.in
 	done > $@.tmp
 	mv $@.tmp $@
 
-$(riscv_gen_srcs): %.cc: insns/%.h insn_template.cc
-	sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/riscv/insn_template.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/riscv/encoding.h,$(subst .cc,,$@))/' > $@
+$(riscv_fast_gen_srcs): %_fast.cc: insns/%.h insn_template.cc
+	sed 's/NAME/$(subst _fast.cc,,$@)/' $(src_dir)/riscv/insn_template.cc | sed 's/TYPE/fast/' | sed 's/OPCODE/$(call get_opcode,$(src_dir)/riscv/encoding.h,$(subst _fast.cc,,$@))/' > $@
+
+$(riscv_logged_gen_srcs): %_logged.cc: insns/%.h insn_template.cc
+	sed 's/NAME/$(subst _logged.cc,,$@)/' $(src_dir)/riscv/insn_template.cc | sed 's/TYPE/logged/' | sed 's/OPCODE/$(call get_opcode,$(src_dir)/riscv/encoding.h,$(subst _logged.cc,,$@))/' > $@
 
 riscv_junk = \
 	$(riscv_gen_srcs) \
diff --git a/riscv/rocc.cc b/riscv/rocc.cc
index f0dd0b2..f68104b 100644
--- a/riscv/rocc.cc
+++ b/riscv/rocc.cc
@@ -1,5 +1,7 @@
 // See LICENSE for license details.
 
+#define DECODE_MACRO_USAGE_LOGGED
+#include "decode_macros.h"
 #include "rocc.h"
 #include "trap.h"
 #include <cstdlib>