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| author | Andrew Waterman <andrew@sifive.com> | 2022-12-29 16:05:39 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-01-03 16:44:42 -0800 |
| commit | 1aac9da38f24c5f8eafe57bfb9a0f7820c1cbaca (patch) | |
| tree | ba7769d7a07dfd64f7a998dc6e8ad3ebd5f65cf8 | |
| parent | b3dfcf1523122cf1fb907fdb75dcdc4d655b7b06 (diff) | |
| download | riscv-isa-sim-1aac9da38f24c5f8eafe57bfb9a0f7820c1cbaca.zip riscv-isa-sim-1aac9da38f24c5f8eafe57bfb9a0f7820c1cbaca.tar.gz riscv-isa-sim-1aac9da38f24c5f8eafe57bfb9a0f7820c1cbaca.tar.bz2 | |
Delete --enable-misaligned configure option
| -rw-r--r-- | config.h.in | 3 | ||||
| -rwxr-xr-x | configure | 16 | ||||
| -rw-r--r-- | riscv/riscv.ac | 5 |
3 files changed, 0 insertions, 24 deletions
diff --git a/config.h.in b/config.h.in index c89b10d..01d776c 100644 --- a/config.h.in +++ b/config.h.in @@ -105,9 +105,6 @@ /* Enable support for running target in either endianness */ #undef RISCV_ENABLE_DUAL_ENDIAN -/* Enable hardware support for misaligned loads and stores */ -#undef RISCV_ENABLE_MISALIGNED - /* Define if subproject MCPPBS_SPROJ_NORM is enabled */ #undef SOFTFLOAT_ENABLED @@ -716,7 +716,6 @@ with_priv with_varch with_target enable_dirty -enable_misaligned enable_dual_endian ' ac_precious_vars='build_alias @@ -1362,8 +1361,6 @@ Optional Features: Enable all optional subprojects --enable-dirty Enable hardware management of PTE accessed and dirty bits - --enable-misaligned Enable hardware support for misaligned loads and - stores --enable-dual-endian Enable support for running target in either endianness @@ -6063,19 +6060,6 @@ $as_echo "#define RISCV_ENABLE_DIRTY /**/" >>confdefs.h fi -# Check whether --enable-misaligned was given. -if test "${enable_misaligned+set}" = set; then : - enableval=$enable_misaligned; -fi - -if test "x$enable_misaligned" = "xyes"; then : - - -$as_echo "#define RISCV_ENABLE_MISALIGNED /**/" >>confdefs.h - - -fi - # Check whether --enable-dual-endian was given. if test "${enable_dual_endian+set}" = set; then : enableval=$enable_dual_endian; diff --git a/riscv/riscv.ac b/riscv/riscv.ac index 70d8438..cb921ef 100644 --- a/riscv/riscv.ac +++ b/riscv/riscv.ac @@ -44,11 +44,6 @@ AS_IF([test "x$enable_dirty" = "xyes"], [ AC_DEFINE([RISCV_ENABLE_DIRTY],,[Enable hardware management of PTE accessed and dirty bits]) ]) -AC_ARG_ENABLE([misaligned], AS_HELP_STRING([--enable-misaligned], [Enable hardware support for misaligned loads and stores])) -AS_IF([test "x$enable_misaligned" = "xyes"], [ - AC_DEFINE([RISCV_ENABLE_MISALIGNED],,[Enable hardware support for misaligned loads and stores]) -]) - AC_ARG_ENABLE([dual-endian], AS_HELP_STRING([--enable-dual-endian], [Enable support for running target in either endianness])) AS_IF([test "x$enable_dual_endian" = "xyes"], [ AC_DEFINE([RISCV_ENABLE_DUAL_ENDIAN],,[Enable support for running target in either endianness]) |