diff options
author | Ryan Buchner <ryan.buchner@arilinc.com> | 2022-05-10 15:22:11 -0700 |
---|---|---|
committer | Ryan Buchner <ryan.buchner@arilinc.com> | 2022-05-11 10:18:58 -0700 |
commit | fc35f34fd0f5307354cc25ae8018cda62f834e25 (patch) | |
tree | 241ec9a824b6b92345ba1d35239bfb22286c4c18 | |
parent | 8e8af2659a7349b9e04a87721c184b3589512482 (diff) | |
download | riscv-isa-sim-fc35f34fd0f5307354cc25ae8018cda62f834e25.zip riscv-isa-sim-fc35f34fd0f5307354cc25ae8018cda62f834e25.tar.gz riscv-isa-sim-fc35f34fd0f5307354cc25ae8018cda62f834e25.tar.bz2 |
Change henvcfg csr to a henvcfg_csr_t
To do so implemented henvcfg_csr_t.
henvcfg.PBMTE will be read only 0 if menvcfg.PBMTE = 0.
-rw-r--r-- | riscv/csrs.cc | 7 | ||||
-rw-r--r-- | riscv/csrs.h | 14 | ||||
-rw-r--r-- | riscv/processor.cc | 2 |
3 files changed, 22 insertions, 1 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 8366d8a..3d6cf91 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -840,6 +840,13 @@ bool masked_csr_t::unlogged_write(const reg_t val) noexcept { } +// implement class henvcfg_csr_t +henvcfg_csr_t::henvcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init, csr_t_p menvcfg): + masked_csr_t(proc, addr, mask, init), + menvcfg(menvcfg) { +} + + // implement class base_atp_csr_t and family base_atp_csr_t::base_atp_csr_t(processor_t* const proc, const reg_t addr): basic_csr_t(proc, addr, 0) { diff --git a/riscv/csrs.h b/riscv/csrs.h index 660ddd1..f6d2c2c 100644 --- a/riscv/csrs.h +++ b/riscv/csrs.h @@ -448,6 +448,20 @@ class masked_csr_t: public basic_csr_t { }; +// henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0 +class henvcfg_csr_t final: public masked_csr_t { + public: + henvcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init, csr_t_p menvcfg); + + reg_t read() const noexcept override { + return (menvcfg->read() | ~MENVCFG_PBMTE) & masked_csr_t::read(); + } + + private: + csr_t_p menvcfg; +}; + + // For satp and vsatp // These are three classes in order to handle the [V]TVM bits permission checks class base_atp_csr_t: public basic_csr_t { diff --git a/riscv/processor.cc b/riscv/processor.cc index 9ce9287..72f2d47 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -387,7 +387,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa) csrmap[CSR_SENVCFG] = senvcfg = std::make_shared<masked_csr_t>(proc, CSR_SENVCFG, senvcfg_mask, 0); const reg_t henvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? HENVCFG_CBCFE | HENVCFG_CBIE : 0) | (proc->extension_enabled(EXT_ZICBOZ) ? HENVCFG_CBZE : 0); - csrmap[CSR_HENVCFG] = henvcfg = std::make_shared<masked_csr_t>(proc, CSR_HENVCFG, henvcfg_mask, 0); + csrmap[CSR_HENVCFG] = henvcfg = std::make_shared<henvcfg_csr_t>(proc, CSR_HENVCFG, henvcfg_mask, 0, menvcfg); serialized = false; |