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author | Tim Newsome <tim@sifive.com> | 2022-05-23 10:20:08 -0700 |
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committer | Tim Newsome <tim@sifive.com> | 2022-05-23 10:20:08 -0700 |
commit | f8874bf55de50d0f0880bea9bf33853c36a432b4 (patch) | |
tree | 5134f83f2c11fa1e18580d777356c099806790d9 | |
parent | 2b43192972cb2f1673b2761be6d0ed7749dd4ee3 (diff) | |
download | riscv-isa-sim-f8874bf55de50d0f0880bea9bf33853c36a432b4.zip riscv-isa-sim-f8874bf55de50d0f0880bea9bf33853c36a432b4.tar.gz riscv-isa-sim-f8874bf55de50d0f0880bea9bf33853c36a432b4.tar.bz2 |
Check address for triggers before the access happens.
Only in slow path right now.
-rw-r--r-- | riscv/mmu.cc | 6 | ||||
-rw-r--r-- | riscv/mmu.h | 16 |
2 files changed, 22 insertions, 0 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index d0a55f0..83ac889 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -143,6 +143,12 @@ void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes, uint32_t xlate { reg_t paddr = translate(addr, len, LOAD, xlate_flags); + if (!matched_trigger) { + matched_trigger = check_trigger_address_before(triggers::OPERATION_LOAD, addr); + if (matched_trigger) + throw *matched_trigger; + } + if (auto host_addr = sim->addr_to_mem(paddr)) { memcpy(bytes, host_addr, len); if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD)) diff --git a/riscv/mmu.h b/riscv/mmu.h index 8964e29..480c633 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -477,6 +477,22 @@ private: return (uint16_t*)(translate_insn_addr(addr).host_offset + addr); } + inline triggers::matched_t *check_trigger_address_before(triggers::operation_t operation, + reg_t address) + { + if (!proc) { + return NULL; + } + triggers::action_t action; + auto match = proc->TM.address_match(&action, operation, address); + if (match == triggers::MATCH_NONE) + return NULL; + if (match == triggers::MATCH_FIRE_BEFORE) { + throw triggers::matched_t(operation, address, 0, action); + } + return new triggers::matched_t(operation, address, 0, action); + } + inline triggers::matched_t *trigger_exception(triggers::operation_t operation, reg_t address, reg_t data) { |