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| author | Scott Johnson <scott.johnson@arilinc.com> | 2021-09-22 18:03:40 -0700 |
|---|---|---|
| committer | Scott Johnson <scott.johnson@arilinc.com> | 2021-09-26 17:17:53 -0700 |
| commit | bfcf4707b301230542816fd7bd71f89d57d3ef16 (patch) | |
| tree | 1adbac86eecb0356df75bac65410b47654e290cf | |
| parent | c3f918afad4e57ba9dcc2eb4c00ebb76e981108a (diff) | |
| download | riscv-isa-sim-bfcf4707b301230542816fd7bd71f89d57d3ef16.zip riscv-isa-sim-bfcf4707b301230542816fd7bd71f89d57d3ef16.tar.gz riscv-isa-sim-bfcf4707b301230542816fd7bd71f89d57d3ef16.tar.bz2 | |
Move dcsr_t definition to csrs.h
In prep for its conversion to csr_t.
| -rw-r--r-- | riscv/csrs.h | 13 | ||||
| -rw-r--r-- | riscv/processor.h | 12 |
2 files changed, 13 insertions, 12 deletions
diff --git a/riscv/csrs.h b/riscv/csrs.h index c9c5584..9cae5c6 100644 --- a/riscv/csrs.h +++ b/riscv/csrs.h @@ -543,4 +543,17 @@ class dpc_csr_t: public epc_csr_t { virtual void verify_permissions(insn_t insn, bool write) const override; }; +typedef struct +{ + uint8_t prv; + bool step; + bool ebreakm; + bool ebreakh; + bool ebreaks; + bool ebreaku; + bool halt; + uint8_t cause; +} dcsr_t; + + #endif diff --git a/riscv/processor.h b/riscv/processor.h index 36422b3..a594f6b 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -37,18 +37,6 @@ typedef std::unordered_map<reg_t, freg_t> commit_log_reg_t; // addr, value, size typedef std::vector<std::tuple<reg_t, uint64_t, uint8_t>> commit_log_mem_t; -typedef struct -{ - uint8_t prv; - bool step; - bool ebreakm; - bool ebreakh; - bool ebreaks; - bool ebreaku; - bool halt; - uint8_t cause; -} dcsr_t; - typedef enum { ACTION_DEBUG_EXCEPTION = MCONTROL_ACTION_DEBUG_EXCEPTION, |