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author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-25 00:11:48 -0700 |
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committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-25 00:11:48 -0700 |
commit | ba69781e5d2bdafc5f8356e246c56261ec838729 (patch) | |
tree | 1f8c0a7b6b5a53f0fab196125fcb57269aedd34f | |
parent | a878edfef23ca7deb3c0698e8c9b1d674ba86cf0 (diff) | |
download | riscv-isa-sim-ba69781e5d2bdafc5f8356e246c56261ec838729.zip riscv-isa-sim-ba69781e5d2bdafc5f8356e246c56261ec838729.tar.gz riscv-isa-sim-ba69781e5d2bdafc5f8356e246c56261ec838729.tar.bz2 |
rvv: fix wrong vill checking
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
-rw-r--r-- | riscv/decode.h | 4 | ||||
-rw-r--r-- | riscv/insns/vl1r_v.h | 2 | ||||
-rw-r--r-- | riscv/insns/vmv_x_s.h | 1 | ||||
-rw-r--r-- | riscv/insns/vmvnfr_v.h | 2 | ||||
-rw-r--r-- | riscv/insns/vs1r_v.h | 2 | ||||
-rw-r--r-- | riscv/insns/vsetvl.h | 2 | ||||
-rw-r--r-- | riscv/insns/vsetvli.h | 2 |
7 files changed, 9 insertions, 6 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 0cc5512..e6e3cb7 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -246,10 +246,12 @@ private: WRITE_VSTATUS; \ dirty_vs_state; \ } while (0); -#define require_vector_for_vsetvl \ +#define require_vector_novtype(is_log) \ do { \ require_vector_vs; \ require_extension('V'); \ + if (is_log) \ + WRITE_VSTATUS; \ dirty_vs_state; \ } while (0); #define require_align(val, pos) require(is_aligned(val, pos)) diff --git a/riscv/insns/vl1r_v.h b/riscv/insns/vl1r_v.h index 09f4040..61e8765 100644 --- a/riscv/insns/vl1r_v.h +++ b/riscv/insns/vl1r_v.h @@ -1,5 +1,5 @@ // vl1r.v vd, (rs1) -require_vector; +require_vector_novtype(true); const reg_t baseAddr = RS1; const reg_t vd = insn.rd(); for (reg_t i = 0; i < P.VU.vlenb; ++i) { diff --git a/riscv/insns/vmv_x_s.h b/riscv/insns/vmv_x_s.h index 086812b..04cad1c 100644 --- a/riscv/insns/vmv_x_s.h +++ b/riscv/insns/vmv_x_s.h @@ -1,4 +1,5 @@ // vmv_x_s: rd = vs2[rs1] +require_vector; require(insn.v_vm() == 1); uint64_t xmask = UINT64_MAX >> (64 - P.get_max_xlen()); reg_t rs1 = RS1; diff --git a/riscv/insns/vmvnfr_v.h b/riscv/insns/vmvnfr_v.h index bafcb4d..51045ce 100644 --- a/riscv/insns/vmvnfr_v.h +++ b/riscv/insns/vmvnfr_v.h @@ -1,5 +1,5 @@ // vmv1r.v vd, vs2 -require_vector; +require_vector_novtype(true); const reg_t baseAddr = RS1; const reg_t vd = insn.rd(); const reg_t vs2 = insn.rs2(); diff --git a/riscv/insns/vs1r_v.h b/riscv/insns/vs1r_v.h index 0dfc537..20dcece 100644 --- a/riscv/insns/vs1r_v.h +++ b/riscv/insns/vs1r_v.h @@ -1,5 +1,5 @@ // vs1r.v vs3, (rs1) -require_vector; +require_vector_novtype(true); const reg_t baseAddr = RS1; const reg_t vs3 = insn.rd(); for (reg_t i = 0; i < P.VU.vlenb; ++i) { diff --git a/riscv/insns/vsetvl.h b/riscv/insns/vsetvl.h index fb3a558..4d03542 100644 --- a/riscv/insns/vsetvl.h +++ b/riscv/insns/vsetvl.h @@ -1,2 +1,2 @@ -require_vector_for_vsetvl; +require_vector_novtype(false); WRITE_RD(P.VU.set_vl(insn.rd(), insn.rs1(), RS1, RS2)); diff --git a/riscv/insns/vsetvli.h b/riscv/insns/vsetvli.h index 56d3a9a..d1f43b5 100644 --- a/riscv/insns/vsetvli.h +++ b/riscv/insns/vsetvli.h @@ -1,2 +1,2 @@ -require_vector_for_vsetvl; +require_vector_novtype(false); WRITE_RD(P.VU.set_vl(insn.rd(), insn.rs1(), RS1, insn.v_zimm11())); |