rvv: support [u]i8 type

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

16 files changed, 59 insertions, 3 deletions

diff --git a/riscv/decode.h b/riscv/decode.h
index 4b99c71..0cc5512 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -2183,15 +2183,20 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
   DEBUG_RVV_FP_VV; \
   VI_VFP_LOOP_END
 
-#define VI_VFP_CVT_SCALE(BODY16, BODY32, is_widen) \
+#define VI_VFP_CVT_SCALE(BODY8, BODY16, BODY32, is_widen) \
   if (is_widen) { \
     VI_CHECK_DSS(false);\
   } else { \
     VI_CHECK_SDS(false); \
   } \
-  require((P.VU.vsew == e16 && p->supports_extension('F')) || \
-          (P.VU.vsew == e32 && p->supports_extension('D'))); \
   switch(P.VU.vsew) { \
+    case e8: {\
+      VI_VFP_LOOP_BASE \
+        BODY8 \
+        set_fp_exceptions; \
+      VI_VFP_LOOP_END \
+      } \
+      break; \
     case e16: {\
       VI_VFP_LOOP_BASE \
         BODY16 \
diff --git a/riscv/insns/vfncvt_f_f_w.h b/riscv/insns/vfncvt_f_f_w.h
index d5d5de6..5ccdcc3 100644
--- a/riscv/insns/vfncvt_f_f_w.h
+++ b/riscv/insns/vfncvt_f_f_w.h
@@ -1,6 +1,9 @@
 // vfncvt.f.f.v vd, vs2, vm
 VI_VFP_CVT_SCALE
 ({
+  require(0);
+},
+{
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<float16_t>(rd_num, i, true) = f32_to_f16(vs2);
 },
diff --git a/riscv/insns/vfncvt_f_x_w.h b/riscv/insns/vfncvt_f_x_w.h
index 25faa1e..9684899 100644
--- a/riscv/insns/vfncvt_f_x_w.h
+++ b/riscv/insns/vfncvt_f_x_w.h
@@ -1,6 +1,9 @@
 // vfncvt.f.x.v vd, vs2, vm
 VI_VFP_CVT_SCALE
 ({
+  require(0);
+},
+{
   auto vs2 = P.VU.elt<int32_t>(rs2_num, i);
   P.VU.elt<float16_t>(rd_num, i, true) = i32_to_f16(vs2);
 },
diff --git a/riscv/insns/vfncvt_f_xu_w.h b/riscv/insns/vfncvt_f_xu_w.h
index a8b62fe..04b2b2b 100644
--- a/riscv/insns/vfncvt_f_xu_w.h
+++ b/riscv/insns/vfncvt_f_xu_w.h
@@ -1,6 +1,9 @@
 // vfncvt.f.xu.v vd, vs2, vm
 VI_VFP_CVT_SCALE
 ({
+  require(0);
+},
+{
   auto vs2 = P.VU.elt<uint32_t>(rs2_num, i);
   P.VU.elt<float16_t>(rd_num, i, true) = ui32_to_f16(vs2);
 },
diff --git a/riscv/insns/vfncvt_rod_f_f_w.h b/riscv/insns/vfncvt_rod_f_f_w.h
index 864b784..bb0b851 100644
--- a/riscv/insns/vfncvt_rod_f_f_w.h
+++ b/riscv/insns/vfncvt_rod_f_f_w.h
@@ -1,6 +1,9 @@
 // vfncvt.rod.f.f.v vd, vs2, vm
 VI_VFP_CVT_SCALE
 ({
+  require(0);
+},
+{
   softfloat_roundingMode = softfloat_round_odd;
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<float16_t>(rd_num, i, true) = f32_to_f16(vs2);
diff --git a/riscv/insns/vfncvt_rtz_x_f_w.h b/riscv/insns/vfncvt_rtz_x_f_w.h
index 70c66d1..63a1842 100644
--- a/riscv/insns/vfncvt_rtz_x_f_w.h
+++ b/riscv/insns/vfncvt_rtz_x_f_w.h
@@ -1,6 +1,10 @@
 // vfncvt.rtz.x.f.w vd, vs2, vm
 VI_VFP_CVT_SCALE
 ({
+  auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
+  P.VU.elt<int8_t>(rd_num, i, true) = f16_to_i8(vs2, softfloat_round_minMag, true);
+},
+{
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<int16_t>(rd_num, i, true) = f32_to_i16(vs2, softfloat_round_minMag, true);
 },
diff --git a/riscv/insns/vfncvt_rtz_xu_f_w.h b/riscv/insns/vfncvt_rtz_xu_f_w.h
index 98f1c4b..9316e22 100644
--- a/riscv/insns/vfncvt_rtz_xu_f_w.h
+++ b/riscv/insns/vfncvt_rtz_xu_f_w.h
@@ -1,6 +1,10 @@
 // vfncvt.rtz.xu.f.w vd, vs2, vm
 VI_VFP_CVT_SCALE
 ({
+  auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
+  P.VU.elt<uint8_t>(rd_num, i, true) = f16_to_ui8(vs2, softfloat_round_minMag, true);
+},
+{
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<uint16_t>(rd_num, i, true) = f32_to_ui16(vs2, softfloat_round_minMag, true);
 },
diff --git a/riscv/insns/vfncvt_x_f_w.h b/riscv/insns/vfncvt_x_f_w.h
index 3ddbb87..aed35e6 100644
--- a/riscv/insns/vfncvt_x_f_w.h
+++ b/riscv/insns/vfncvt_x_f_w.h
@@ -1,6 +1,10 @@
 // vfncvt.x.f.w vd, vs2, vm
 VI_VFP_CVT_SCALE
 ({
+  auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
+  P.VU.elt<int8_t>(rd_num, i, true) = f16_to_i8(vs2, STATE.frm, true);
+},
+{
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<int16_t>(rd_num, i, true) = f32_to_i16(vs2, STATE.frm, true);
 },
diff --git a/riscv/insns/vfncvt_xu_f_w.h b/riscv/insns/vfncvt_xu_f_w.h
index 3b7d473..c46b620 100644
--- a/riscv/insns/vfncvt_xu_f_w.h
+++ b/riscv/insns/vfncvt_xu_f_w.h
@@ -1,6 +1,10 @@
 // vfncvt.xu.f.w vd, vs2, vm
 VI_VFP_CVT_SCALE
 ({
+  auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
+  P.VU.elt<uint8_t>(rd_num, i, true) = f16_to_ui8(vs2, STATE.frm, true);
+},
+{
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<uint16_t>(rd_num, i, true) = f32_to_ui16(vs2, STATE.frm, true);
 },
diff --git a/riscv/insns/vfwcvt_f_f_v.h b/riscv/insns/vfwcvt_f_f_v.h
index abb68a4..2d418a2 100644
--- a/riscv/insns/vfwcvt_f_f_v.h
+++ b/riscv/insns/vfwcvt_f_f_v.h
@@ -1,6 +1,9 @@
 // vfwcvt.f.f.v vd, vs2, vm
 VI_VFP_CVT_SCALE
 ({
+  require(0);
+},
+{
   auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
   P.VU.elt<float32_t>(rd_num, i, true) = f16_to_f32(vs2);
 },
diff --git a/riscv/insns/vfwcvt_f_x_v.h b/riscv/insns/vfwcvt_f_x_v.h
index 62cd8e8..90978bc 100644
--- a/riscv/insns/vfwcvt_f_x_v.h
+++ b/riscv/insns/vfwcvt_f_x_v.h
@@ -1,6 +1,10 @@
 // vfwcvt.f.x.v vd, vs2, vm
 VI_VFP_CVT_SCALE
 ({
+  auto vs2 = P.VU.elt<int8_t>(rs2_num, i);
+  P.VU.elt<float16_t>(rd_num, i, true) = i32_to_f16(vs2);
+},
+{
   auto vs2 = P.VU.elt<int16_t>(rs2_num, i);
   P.VU.elt<float32_t>(rd_num, i, true) = i32_to_f32(vs2);
 },
diff --git a/riscv/insns/vfwcvt_f_xu_v.h b/riscv/insns/vfwcvt_f_xu_v.h
index 36a81ed..7a9be7d 100644
--- a/riscv/insns/vfwcvt_f_xu_v.h
+++ b/riscv/insns/vfwcvt_f_xu_v.h
@@ -1,6 +1,10 @@
 // vfwcvt.f.xu.v vd, vs2, vm
 VI_VFP_CVT_SCALE
 ({
+  auto vs2 = P.VU.elt<uint8_t>(rs2_num, i);
+  P.VU.elt<float16_t>(rd_num, i, true) = ui32_to_f16(vs2);
+},
+{
   auto vs2 = P.VU.elt<uint16_t>(rs2_num, i);
   P.VU.elt<float32_t>(rd_num, i, true) = ui32_to_f32(vs2);
 },
diff --git a/riscv/insns/vfwcvt_rtz_x_f_v.h b/riscv/insns/vfwcvt_rtz_x_f_v.h
index ad3a90d..17946f9 100644
--- a/riscv/insns/vfwcvt_rtz_x_f_v.h
+++ b/riscv/insns/vfwcvt_rtz_x_f_v.h
@@ -1,6 +1,9 @@
 // vfwcvt.rtz.x.f.v vd, vs2, vm
 VI_VFP_CVT_SCALE
 ({
+  require(0);
+},
+{
   auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
   P.VU.elt<int32_t>(rd_num, i, true) = f16_to_i32(vs2, softfloat_round_minMag, true);
 },
diff --git a/riscv/insns/vfwcvt_rtz_xu_f_v.h b/riscv/insns/vfwcvt_rtz_xu_f_v.h
index 297008f..9d5e235 100644
--- a/riscv/insns/vfwcvt_rtz_xu_f_v.h
+++ b/riscv/insns/vfwcvt_rtz_xu_f_v.h
@@ -1,6 +1,9 @@
 // vfwcvt.rtz,xu.f.v vd, vs2, vm
 VI_VFP_CVT_SCALE
 ({
+  require(0);
+},
+{
   auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
   P.VU.elt<uint32_t>(rd_num, i, true) = f16_to_ui32(vs2, softfloat_round_minMag, true);
 },
diff --git a/riscv/insns/vfwcvt_x_f_v.h b/riscv/insns/vfwcvt_x_f_v.h
index 9b79893..879f980 100644
--- a/riscv/insns/vfwcvt_x_f_v.h
+++ b/riscv/insns/vfwcvt_x_f_v.h
@@ -1,6 +1,9 @@
 // vfwcvt.x.f.v vd, vs2, vm
 VI_VFP_CVT_SCALE
 ({
+  require(0);
+},
+{
   auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
   P.VU.elt<int32_t>(rd_num, i, true) = f16_to_i32(vs2, STATE.frm, true);
 },
diff --git a/riscv/insns/vfwcvt_xu_f_v.h b/riscv/insns/vfwcvt_xu_f_v.h
index bfe16ff..70ce696 100644
--- a/riscv/insns/vfwcvt_xu_f_v.h
+++ b/riscv/insns/vfwcvt_xu_f_v.h
@@ -1,6 +1,9 @@
 // vfwcvt.xu.f.v vd, vs2, vm
 VI_VFP_CVT_SCALE
 ({
+  require(0);
+},
+{
   auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
   P.VU.elt<uint32_t>(rd_num, i, true) = f16_to_ui32(vs2, STATE.frm, true);
 },