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authorChih-Min Chao <chihmin.chao@sifive.com>2020-05-21 00:53:12 -0700
committerChih-Min Chao <chihmin.chao@sifive.com>2020-05-21 05:49:28 -0700
commit8371e72b26d70c14f38de4e20543a51bb396d42c (patch)
treeeedd364c5361edf93ec98e3d5a611fb09edf1d26
parent47f1c5247b606ae82b0ea74cba390301995e3754 (diff)
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rvv: fix index checking
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
-rw-r--r--riscv/decode.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/riscv/decode.h b/riscv/decode.h
index 69bd848..942c17c 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -456,14 +456,18 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
P.VU.veew = elt_width; \
P.VU.vemul = ((float)P.VU.veew / P.VU.vsew * P.VU.vflmul); \
require(P.VU.vemul >= 0.125 && P.VU.vemul <= 8); \
+ reg_t emul = P.VU.vemul < 1 ? 1 : P.VU.vemul; \
reg_t flmul = P.VU.vflmul < 1 ? 1 : P.VU.vflmul; \
require_align(insn.rd(), P.VU.vflmul); \
require_align(insn.rs2(), P.VU.vemul); \
require((nf * flmul) <= (NVPR / 4) && \
- (insn.rd() + nf * flmul) <= NVPR); \
+ (insn.rd() + nf * flmul) <= NVPR && \
+ (insn.rs2() + nf * emul) <= NVPR); \
#define VI_CHECK_LD_INDEX(elt_width) \
VI_CHECK_ST_INDEX(elt_width); \
+ if (P.VU.vemul != P.VU.vflmul) \
+ require_noover(insn.rd(), P.VU.vflmul, insn.rs2(), P.VU.vemul); \
if (insn.v_nf() > 0) {\
require_noover(insn.rd(), P.VU.vflmul, insn.rs2(), P.VU.vemul); \
require_noover(vd, nf, insn.rs2(), 1); \