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author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-21 23:52:50 -0700 |
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committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-22 00:19:53 -0700 |
commit | 18e03d0e515eeb38e7f11cf7bb580df83d51f114 (patch) | |
tree | b43c63226643d93508faf6db6d4862df29dc0599 | |
parent | 5e5fa12bdf617b0a4537fd6b0da49816cd05f1c1 (diff) | |
download | riscv-isa-sim-18e03d0e515eeb38e7f11cf7bb580df83d51f114.zip riscv-isa-sim-18e03d0e515eeb38e7f11cf7bb580df83d51f114.tar.gz riscv-isa-sim-18e03d0e515eeb38e7f11cf7bb580df83d51f114.tar.bz2 |
rvv: disasm: fix vsetvli
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
-rw-r--r-- | spike_main/disasm.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc index 0c13cdb..5ad2a0b 100644 --- a/spike_main/disasm.cc +++ b/spike_main/disasm.cc @@ -340,7 +340,7 @@ struct : public arg_t { } s << ", m" << lmul_str; } else { - s << ", m" << lmul; + s << ", m" << (1 << lmul); } s << ", " << vta << ", " << vma; return s.str(); |