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| author | Andrew Waterman <andrew@sifive.com> | 2023-05-09 15:15:18 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-05-09 15:15:18 -0700 |
| commit | c10ed407cab8be2cbe993323952aa4fba9985b80 (patch) | |
| tree | fc778419266a71b075d26e8cde6d4ac011fc7ddf | |
| parent | 64532f9678db1fc170f57c272adaa4e698cd354c (diff) | |
| parent | b07f893609df80d7bcaee470d041221bdea8c920 (diff) | |
| download | riscv-isa-sim-c10ed407cab8be2cbe993323952aa4fba9985b80.zip riscv-isa-sim-c10ed407cab8be2cbe993323952aa4fba9985b80.tar.gz riscv-isa-sim-c10ed407cab8be2cbe993323952aa4fba9985b80.tar.bz2 | |
Merge pull request #1356 from ptomsich/ptomsich/1355-fix-fleq-fltq-exceptions
Zfa: fix missing set_fp_exceptions for fleq/fltq
| -rw-r--r-- | riscv/insns/fleq_d.h | 1 | ||||
| -rw-r--r-- | riscv/insns/fleq_h.h | 1 | ||||
| -rw-r--r-- | riscv/insns/fleq_q.h | 1 | ||||
| -rw-r--r-- | riscv/insns/fleq_s.h | 1 | ||||
| -rw-r--r-- | riscv/insns/fltq_d.h | 1 | ||||
| -rw-r--r-- | riscv/insns/fltq_h.h | 1 | ||||
| -rw-r--r-- | riscv/insns/fltq_q.h | 1 | ||||
| -rw-r--r-- | riscv/insns/fltq_s.h | 1 |
8 files changed, 8 insertions, 0 deletions
diff --git a/riscv/insns/fleq_d.h b/riscv/insns/fleq_d.h index 762e147..5ceb967 100644 --- a/riscv/insns/fleq_d.h +++ b/riscv/insns/fleq_d.h @@ -2,3 +2,4 @@ require_extension('D'); require_extension(EXT_ZFA); require_fp; WRITE_RD(f64_le_quiet(FRS1_D, FRS2_D)); +set_fp_exceptions; diff --git a/riscv/insns/fleq_h.h b/riscv/insns/fleq_h.h index 7e6db59..7e6fd26 100644 --- a/riscv/insns/fleq_h.h +++ b/riscv/insns/fleq_h.h @@ -2,3 +2,4 @@ require_extension(EXT_ZFH); require_extension(EXT_ZFA); require_fp; WRITE_RD(f16_le_quiet(FRS1_H, FRS2_H)); +set_fp_exceptions; diff --git a/riscv/insns/fleq_q.h b/riscv/insns/fleq_q.h index 8533d11..f80a32b 100644 --- a/riscv/insns/fleq_q.h +++ b/riscv/insns/fleq_q.h @@ -2,3 +2,4 @@ require_extension('Q'); require_extension(EXT_ZFA); require_fp; WRITE_RD(f128_le_quiet(f128(FRS1), f128(FRS2))); +set_fp_exceptions; diff --git a/riscv/insns/fleq_s.h b/riscv/insns/fleq_s.h index 8c0a909..e3dc03f 100644 --- a/riscv/insns/fleq_s.h +++ b/riscv/insns/fleq_s.h @@ -2,3 +2,4 @@ require_extension('F'); require_extension(EXT_ZFA); require_fp; WRITE_RD(f32_le_quiet(FRS1_F, FRS2_F)); +set_fp_exceptions; diff --git a/riscv/insns/fltq_d.h b/riscv/insns/fltq_d.h index c7ec9f1..7d116d5 100644 --- a/riscv/insns/fltq_d.h +++ b/riscv/insns/fltq_d.h @@ -2,3 +2,4 @@ require_extension('D'); require_extension(EXT_ZFA); require_fp; WRITE_RD(f64_lt_quiet(FRS1_D, FRS2_D)); +set_fp_exceptions; diff --git a/riscv/insns/fltq_h.h b/riscv/insns/fltq_h.h index 84d880a..177e545 100644 --- a/riscv/insns/fltq_h.h +++ b/riscv/insns/fltq_h.h @@ -2,3 +2,4 @@ require_extension(EXT_ZFH); require_extension(EXT_ZFA); require_fp; WRITE_RD(f16_lt_quiet(FRS1_H, FRS2_H)); +set_fp_exceptions; diff --git a/riscv/insns/fltq_q.h b/riscv/insns/fltq_q.h index a65ca76..208d248 100644 --- a/riscv/insns/fltq_q.h +++ b/riscv/insns/fltq_q.h @@ -2,3 +2,4 @@ require_extension('Q'); require_extension(EXT_ZFA); require_fp; WRITE_RD(f128_lt_quiet(f128(FRS1), f128(FRS2))); +set_fp_exceptions; diff --git a/riscv/insns/fltq_s.h b/riscv/insns/fltq_s.h index 1ee0983..b2e1df5 100644 --- a/riscv/insns/fltq_s.h +++ b/riscv/insns/fltq_s.h @@ -2,3 +2,4 @@ require_extension('F'); require_extension(EXT_ZFA); require_fp; WRITE_RD(f32_lt_quiet(FRS1_F, FRS2_F)); +set_fp_exceptions; |