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| author | rbuchner <ryan.buchner@arilinc.com> | 2023-05-01 12:42:28 -0700 |
|---|---|---|
| committer | rbuchner <ryan.buchner@arilinc.com> | 2023-05-11 23:00:59 -0700 |
| commit | 850600792ec04756f7720a9b376cfb2d8ad6c917 (patch) | |
| tree | bd8f192a0915279c41f08b196125184d7626645d | |
| parent | 125c4d6a6400eef6365d8379efef1330c429f64e (diff) | |
| download | riscv-isa-sim-850600792ec04756f7720a9b376cfb2d8ad6c917.zip riscv-isa-sim-850600792ec04756f7720a9b376cfb2d8ad6c917.tar.gz riscv-isa-sim-850600792ec04756f7720a9b376cfb2d8ad6c917.tar.bz2 | |
Use access_info.effective_virt when failed mmio_store (i.e. device detects access fault)
Fixes case 3 from https://github.com/riscv-software-src/riscv-isa-sim/issues/872
| -rw-r--r-- | riscv/mmu.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index cf77325..a524035 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -268,7 +268,7 @@ void mmu_t::store_slow_path_intrapage(reg_t len, const uint8_t* bytes, mem_acces else if (!access_info.flags.is_special_access()) refill_tlb(addr, paddr, host_addr, STORE); } else if (!mmio_store(paddr, len, bytes)) { - throw trap_store_access_fault((proc) ? proc->state.v : false, addr, 0, 0); + throw trap_store_access_fault(access_info.effective_virt, addr, 0, 0); } } } |