diff options
author | rbuchner <ryan.buchner@arilinc.com> | 2023-04-19 16:20:56 -0700 |
---|---|---|
committer | rbuchner <ryan.buchner@arilinc.com> | 2023-05-11 23:00:59 -0700 |
commit | 36b8c12e9f4d92f3cb97daf4ea0613436724438f (patch) | |
tree | 9267c5e31ff001f3c37596f7e993e34772ca4d0e | |
parent | 4b9996bad9a3327b13056f21b7b2e03fdc41f65a (diff) | |
download | riscv-isa-sim-36b8c12e9f4d92f3cb97daf4ea0613436724438f.zip riscv-isa-sim-36b8c12e9f4d92f3cb97daf4ea0613436724438f.tar.gz riscv-isa-sim-36b8c12e9f4d92f3cb97daf4ea0613436724438f.tar.bz2 |
Add split_misaligned_access() to mem_access_info_t
-rw-r--r-- | riscv/mmu.cc | 4 | ||||
-rw-r--r-- | riscv/mmu.h | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index f40ce30..734e8cd 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -239,7 +239,7 @@ void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes, xlate_flags_t reg_t len_page0 = std::min(len, PGSIZE - addr % PGSIZE); load_slow_path_intrapage(len_page0, bytes, access_info); if (len_page0 != len) - load_slow_path_intrapage(len - len_page0, bytes + len_page0, generate_access_info(addr + len_page0, LOAD, xlate_flags)); + load_slow_path_intrapage(len - len_page0, bytes + len_page0, access_info.split_misaligned_access(len_page0)); } check_triggers(triggers::OPERATION_LOAD, addr, reg_from_bytes(len, bytes)); @@ -289,7 +289,7 @@ void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes, xlate_f reg_t len_page0 = std::min(len, PGSIZE - addr % PGSIZE); store_slow_path_intrapage(len_page0, bytes, access_info, actually_store); if (len_page0 != len) - store_slow_path_intrapage(len - len_page0, bytes + len_page0, generate_access_info(addr + len_page0, STORE, xlate_flags), actually_store); + store_slow_path_intrapage(len - len_page0, bytes + len_page0, access_info.split_misaligned_access(len_page0), actually_store); } else { store_slow_path_intrapage(len, bytes, access_info, actually_store); } diff --git a/riscv/mmu.h b/riscv/mmu.h index 7d14ad5..2f93863 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -54,6 +54,10 @@ struct mem_access_info_t { const bool effective_virt; const xlate_flags_t flags; const access_type type; + + mem_access_info_t split_misaligned_access(reg_t offset) const { + return {vaddr + offset, effective_priv, effective_virt, flags, type}; + } }; void throw_access_exception(bool virt, reg_t addr, access_type type); |