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author | Andrew Waterman <andrew@sifive.com> | 2023-04-19 14:59:27 -0700 |
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committer | GitHub <noreply@github.com> | 2023-04-19 14:59:27 -0700 |
commit | 0835bd7729f317a009d9bec775f8e4bf420f93a7 (patch) | |
tree | 4a5c5b285686a017fa20f5653d309b614500451f | |
parent | 3f7937e25ad051dd0c65da8461d209f3cf00a4cf (diff) | |
parent | 64dfca6becd82965793e00c1439f2f62ca260986 (diff) | |
download | riscv-isa-sim-0835bd7729f317a009d9bec775f8e4bf420f93a7.zip riscv-isa-sim-0835bd7729f317a009d9bec775f8e4bf420f93a7.tar.gz riscv-isa-sim-0835bd7729f317a009d9bec775f8e4bf420f93a7.tar.bz2 |
Merge pull request #1332 from riscv-software-src/fix-1326
Partially revert #1326
-rw-r--r-- | riscv/v_ext_macros.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h index a0d8322..e00b0c0 100644 --- a/riscv/v_ext_macros.h +++ b/riscv/v_ext_macros.h @@ -341,12 +341,12 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) type_usew_t<x>::type vs2 = P.VU.elt<type_usew_t<x>::type>(rs2_num, i); #define VV_PARAMS(x) \ - type_sew_t<x>::type &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); \ + type_sew_t<x>::type UNUSED &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); \ type_sew_t<x>::type vs1 = P.VU.elt<type_sew_t<x>::type>(rs1_num, i); \ type_sew_t<x>::type UNUSED vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i); #define VX_PARAMS(x) \ - type_sew_t<x>::type &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); \ + type_sew_t<x>::type UNUSED &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); \ type_sew_t<x>::type rs1 = (type_sew_t<x>::type)RS1; \ type_sew_t<x>::type UNUSED vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i); |