diff options
| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-07-12 12:43:30 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-07-12 12:43:30 -0700 |
| commit | da0bc312aefa12960d65dd0e12aa87ad9a771f2d (patch) | |
| tree | 1005eb49b9fb2d60a7257b01074d8f89a36931d7 | |
| parent | 1b797b1aac81b318900bd11065eb64762f32894f (diff) | |
| download | riscv-isa-sim-da0bc312aefa12960d65dd0e12aa87ad9a771f2d.zip riscv-isa-sim-da0bc312aefa12960d65dd0e12aa87ad9a771f2d.tar.gz riscv-isa-sim-da0bc312aefa12960d65dd0e12aa87ad9a771f2d.tar.bz2 | |
Don't treat RVC NOP as illegal instruction
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 50906f6..8c89e3f 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -565,7 +565,7 @@ void processor_t::build_opcode_map() std::sort(instructions.begin(), instructions.end(), cmp()); for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++) - opcode_cache[i] = {1, 0, &illegal_instruction, &illegal_instruction}; + opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction}; } void processor_t::register_extension(extension_t* x) |