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author | Tim Newsome <tim@sifive.com> | 2016-07-01 09:51:26 -0700 |
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committer | Tim Newsome <tim@sifive.com> | 2016-07-01 09:51:26 -0700 |
commit | 6f64a1f72ebd4888d61f324bc68c5becf60d66d9 (patch) | |
tree | d0460b06560918b67bcf02c2455daf09dada2515 | |
parent | 03b8bad375217fbc2143046e8caad9d80301abdb (diff) | |
download | riscv-isa-sim-6f64a1f72ebd4888d61f324bc68c5becf60d66d9.zip riscv-isa-sim-6f64a1f72ebd4888d61f324bc68c5becf60d66d9.tar.gz riscv-isa-sim-6f64a1f72ebd4888d61f324bc68c5becf60d66d9.tar.bz2 |
Remove debug printf that was cluttering up output.
-rw-r--r-- | riscv/gdbserver.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/riscv/gdbserver.cc b/riscv/gdbserver.cc index 140cdd5..370dd9a 100644 --- a/riscv/gdbserver.cc +++ b/riscv/gdbserver.cc @@ -392,7 +392,6 @@ class halt_op_t : public operation_t case ST_DPC: gs.dpc = gs.dr_read(SLOT_DATA0); - fprintf(stderr, "dpc=0x%lx\n", gs.dpc); gs.dr_write32(0, csrr(S0, CSR_MSTATUS)); gs.dr_write_store(1, S0, SLOT_DATA0); gs.dr_write_jump(2); |