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author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-07-12 12:43:07 -0700 |
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committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-07-12 12:43:07 -0700 |
commit | 1b797b1aac81b318900bd11065eb64762f32894f (patch) | |
tree | 8ab83a8509459d549d0267e39c7c4e3c8220671e | |
parent | e10d2def7d5d8b162c0c0f0922ddc2a46fc24ea2 (diff) | |
download | riscv-isa-sim-1b797b1aac81b318900bd11065eb64762f32894f.zip riscv-isa-sim-1b797b1aac81b318900bd11065eb64762f32894f.tar.gz riscv-isa-sim-1b797b1aac81b318900bd11065eb64762f32894f.tar.bz2 |
Fix page table walker not respecting valid bit
-rw-r--r-- | riscv/mmu.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 602b090..4b7166f 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -153,7 +153,7 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode) base = ppn << PGSHIFT; } else if ((pte & PTE_U) ? supervisor && pum : !supervisor) { break; - } else if (!(pte & PTE_R) && (pte & PTE_W)) { // reserved + } else if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) { break; } else if (type == FETCH ? !(pte & PTE_X) : type == LOAD ? !(pte & PTE_R) && !(mxr && (pte & PTE_X)) : |