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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-28 19:37:29 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-28 22:59:58 -0700 |
| commit | 5ea3ef76d2aadab3a95b8b35330edb22232e9c9c (patch) | |
| tree | e4edceb75d5669acd7d8b891cca1bf5cd0fe40ff | |
| parent | 09adc65e7db92c651b26e376b964efec585cc268 (diff) | |
| download | riscv-isa-sim-5ea3ef76d2aadab3a95b8b35330edb22232e9c9c.zip riscv-isa-sim-5ea3ef76d2aadab3a95b8b35330edb22232e9c9c.tar.gz riscv-isa-sim-5ea3ef76d2aadab3a95b8b35330edb22232e9c9c.tar.bz2 | |
rvv: use zvqmac to enable vector qmac
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | riscv/decode.h | 1 | ||||
| -rw-r--r-- | riscv/processor.cc | 5 |
2 files changed, 6 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index ff1579a..dbe6f0e 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -520,6 +520,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) #define VI_CHECK_QSS(is_vs1) \ require_vector;\ + p->supports_extension(EXT_ZVQMAC); \ require(P.VU.vflmul <= 2); \ require(P.VU.vsew * 4 <= P.VU.ELEN); \ require_align(insn.rd(), P.VU.vflmul * 4); \ diff --git a/riscv/processor.cc b/riscv/processor.cc index 757e7ad..0b4ca65 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -261,6 +261,8 @@ void processor_t::parse_isa_string(const char* str) extension_table[EXT_ZVAMO] = true; } else if (ext_str == "zvlsseg") { extension_table[EXT_ZVLSSEG] = true; + } else if (ext_str == "zvqmac") { + extension_table[EXT_ZVQMAC] = true; } else { sprintf(error_msg, "unsupported extension '%s'", ext_str.c_str()); bad_isa_string(str, error_msg); @@ -293,6 +295,9 @@ void processor_t::parse_isa_string(const char* str) if (supports_extension(EXT_ZVLSSEG) && !supports_extension('V')) bad_isa_string(str, "'Zvlsseg' extension requires 'V'"); + + if (supports_extension(EXT_ZVQMAC) && !supports_extension('V')) + bad_isa_string(str, "'Zvqmac' extension requires 'V'"); } void state_t::reset(reg_t max_isa) |