rvv: apply new overlapping and align macro

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

15 files changed, 77 insertions, 87 deletions

diff --git a/riscv/decode.h b/riscv/decode.h
index 8400ba2..ff1579a 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -438,20 +438,18 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
 
 #define VI_NARROW_CHECK_COMMON \
   require_vector;\
-  require(P.VU.vlmul <= 4); \
+  require(P.VU.vflmul <= 4); \
   require(P.VU.vsew * 2 <= P.VU.ELEN); \
-  require((insn.rs2() & (P.VU.vlmul * 2 - 1)) == 0); \
-  require((insn.rd() & (P.VU.vlmul - 1)) == 0); \
-  if (insn.v_vm() == 0 && P.VU.vlmul > 1) \
-    require(insn.rd() != 0);
+  require_align(insn.rs2(), P.VU.vflmul * 2); \
+  require_align(insn.rd(), P.VU.vflmul); \
+  require_vm; \
 
 #define VI_WIDE_CHECK_COMMON \
   require_vector;\
-  require(P.VU.vlmul <= 4); \
+  require(P.VU.vflmul <= 4); \
   require(P.VU.vsew * 2 <= P.VU.ELEN); \
-  require((insn.rd() & (P.VU.vlmul * 2 - 1)) == 0); \
-  if (insn.v_vm() == 0) \
-    require(insn.rd() != 0);
+  require_align(insn.rd(), P.VU.vflmul * 2); \
+  require_vm; \
 
 #define VI_CHECK_ST_INDEX(elt_width) \
   require_vector; \
@@ -478,24 +476,21 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
   require_vm; \
 
 #define VI_CHECK_MSS(is_vs1) \
-  if (P.VU.vlmul > 1) { \
-    require(!is_overlapped(insn.rd(), 1, insn.rs2(), P.VU.vlmul)); \
-    require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \
-    if (is_vs1) {\
-      require(!is_overlapped(insn.rd(), 1, insn.rs1(), P.VU.vlmul)); \
-      require((insn.rs1() & (P.VU.vlmul - 1)) == 0); \
-    } \
-  }
+  require_noover(insn.rd(), 1, insn.rs2(), P.VU.vflmul); \
+  require_align(insn.rs2(), P.VU.vflmul); \
+  if (is_vs1) {\
+    require_noover(insn.rd(), 1, insn.rs1(), P.VU.vflmul); \
+    require_align(insn.rs1(), P.VU.vflmul); \
+  } \
 
 #define VI_CHECK_SSS(is_vs1) \
-  if (P.VU.vlmul > 1) { \
-    require((insn.rd() & (P.VU.vlmul - 1)) == 0); \
-    require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \
+  require_vm; \
+  if (P.VU.vflmul > 1) { \
+    require_align(insn.rd(), P.VU.vflmul); \
+    require_align(insn.rs2(), P.VU.vflmul); \
     if (is_vs1) { \
-      require((insn.rs1() & (P.VU.vlmul - 1)) == 0); \
+      require_align(insn.rs1(), P.VU.vflmul); \
     } \
-    if (insn.v_vm() == 0) \
-      require(insn.rd() != 0); \
   }
 
 #define VI_CHECK_STORE(elt_width) \
@@ -516,55 +511,52 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
 
 #define VI_CHECK_DSS(is_vs1) \
   VI_WIDE_CHECK_COMMON; \
-  require(!is_overlapped(insn.rd(), P.VU.vlmul * 2, insn.rs2(), P.VU.vlmul)); \
-  require((insn.rd() & (P.VU.vlmul * 2 - 1)) == 0); \
-  require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \
+  require_noover(insn.rd(), P.VU.vflmul * 2, insn.rs2(), P.VU.vflmul); \
+  require_align(insn.rs2(), P.VU.vflmul); \
   if (is_vs1) {\
-     require(!is_overlapped(insn.rd(), P.VU.vlmul * 2, insn.rs1(), P.VU.vlmul)); \
-     require((insn.rs1() & (P.VU.vlmul - 1)) == 0); \
+     require_noover(insn.rd(), P.VU.vflmul * 2, insn.rs1(), P.VU.vflmul); \
+     require_align(insn.rs1(), P.VU.vflmul); \
   }
 
 #define VI_CHECK_QSS(is_vs1) \
   require_vector;\
-  require(P.VU.vlmul <= 2); \
+  require(P.VU.vflmul <= 2); \
   require(P.VU.vsew * 4 <= P.VU.ELEN); \
-  require((insn.rd() & (P.VU.vlmul * 4 - 1)) == 0); \
-  if (insn.v_vm() == 0) \
-    require(insn.rd() != 0); \
-  require(!is_overlapped(insn.rd(), P.VU.vlmul * 4, insn.rs2(), P.VU.vlmul)); \
-  require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \
+  require_align(insn.rd(), P.VU.vflmul * 4); \
+  require_vm; \
+  require_noover(insn.rd(), P.VU.vflmul * 4, insn.rs2(), P.VU.vflmul); \
+  require_align(insn.rs2(), P.VU.vflmul); \
   if (is_vs1) {\
-     require(!is_overlapped(insn.rd(), P.VU.vlmul * 4, insn.rs1(), P.VU.vlmul)); \
-     require((insn.rs1() & (P.VU.vlmul - 1)) == 0); \
+     require_noover(insn.rd(), P.VU.vflmul * 4, insn.rs1(), P.VU.vflmul); \
+     require_align(insn.rs1(), P.VU.vflmul); \
   }
 
 #define VI_CHECK_DDS(is_rs) \
   VI_WIDE_CHECK_COMMON; \
-  require((insn.rs2() & (P.VU.vlmul * 2 - 1)) == 0); \
+  require_align(insn.rs2(), P.VU.vflmul * 2); \
   if (is_rs) { \
-     require(!is_overlapped(insn.rd(), P.VU.vlmul * 2, insn.rs1(), P.VU.vlmul)); \
-     require((insn.rs1() & (P.VU.vlmul - 1)) == 0); \
+     require_noover(insn.rd(), P.VU.vflmul * 2, insn.rs1(), P.VU.vflmul); \
+     require_align(insn.rs1(), P.VU.vflmul); \
   }
 
 #define VI_CHECK_SDS(is_vs1) \
   VI_NARROW_CHECK_COMMON; \
-  require(!is_overlapped(insn.rd(), P.VU.vlmul, insn.rs2(), P.VU.vlmul * 2)); \
+  require_noover(insn.rd(), P.VU.vflmul, insn.rs2(), P.VU.vflmul * 2); \
   if (is_vs1) \
-    require((insn.rs1() & (P.VU.vlmul - 1)) == 0); \
+    require_align(insn.rs1(), P.VU.vflmul); \
 
 #define VI_CHECK_REDUCTION(is_wide) \
   require_vector;\
   if (is_wide) {\
     require(P.VU.vsew * 2 <= P.VU.ELEN); \
   } \
-  require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \
+  require_align(insn.rs2(), P.VU.vflmul); \
   require(P.VU.vstart == 0); \
 
 #define VI_CHECK_SLIDE(is_over) \
-  require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \
-  require((insn.rd() & (P.VU.vlmul - 1)) == 0); \
-  if (insn.v_vm() == 0 && P.VU.vlmul > 1) \
-    require(insn.rd() != 0); \
+  require_align(insn.rs2(), P.VU.vflmul); \
+  require_align(insn.rd(), P.VU.vflmul); \
+  require_vm; \
   if (is_over) \
     require(insn.rd() != insn.rs2()); \
 
@@ -573,7 +565,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
 // vector: loop header and end helper
 //
 #define VI_GENERAL_LOOP_BASE \
-  require(P.VU.vsew == e8 || P.VU.vsew == e16 || P.VU.vsew == e32 || P.VU.vsew == e64); \
+  require(P.VU.vsew >= e8 && P.VU.vsew <= e64); \
   require_vector;\
   reg_t vl = P.VU.vl; \
   reg_t sew = P.VU.vsew; \
@@ -598,7 +590,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
   P.VU.vstart = 0; 
 
 #define VI_LOOP_CMP_BASE \
-  require(P.VU.vsew == e8 || P.VU.vsew == e16 || P.VU.vsew == e32 || P.VU.vsew == e64); \
+  require(P.VU.vsew >= e8 && P.VU.vsew <= e64); \
   require_vector;\
   reg_t vl = P.VU.vl; \
   reg_t sew = P.VU.vsew; \
@@ -634,7 +626,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
 #define VI_LOOP_NSHIFT_BASE \
   VI_GENERAL_LOOP_BASE; \
   VI_LOOP_ELEMENT_SKIP({\
-    require(!(insn.rd() == 0 && P.VU.vlmul > 1));\
+    require(!(insn.rd() == 0 && P.VU.vflmul > 1));\
   });
 
 
@@ -909,7 +901,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
 
 // reduction loop - signed
 #define VI_LOOP_REDUCTION_BASE(x) \
-  require(x == e8 || x == e16 || x == e32 || x == e64); \
+  require(x >= e8 && x <= e64); \
   reg_t vl = P.VU.vl; \
   reg_t rd_num = insn.rd(); \
   reg_t rs1_num = insn.rs1(); \
@@ -940,7 +932,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
 
 // reduction loop - unsgied
 #define VI_ULOOP_REDUCTION_BASE(x) \
-  require(x == e8 || x == e16 || x == e32 || x == e64); \
+  require(x >= e8 && x <= e64); \
   reg_t vl = P.VU.vl; \
   reg_t rd_num = insn.rd(); \
   reg_t rs1_num = insn.rs1(); \
@@ -969,6 +961,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
     REDUCTION_ULOOP(e64, BODY) \
   }
 
+
 // genearl VXI signed/unsgied loop
 #define VI_VV_ULOOP(BODY) \
   VI_CHECK_SSS(true) \
@@ -1410,7 +1403,7 @@ VI_LOOP_END
   VI_LOOP_END
 
 #define VI_VV_LOOP_WITH_CARRY(BODY) \
-  require(P.VU.vlmul == 1 || insn.rd() != 0); \
+  require(insn.rd() != 0); \
   VI_CHECK_SSS(true); \
   VI_GENERAL_LOOP_BASE \
   VI_MASK_VARS \
@@ -1430,7 +1423,7 @@ VI_LOOP_END
   VI_LOOP_END
 
 #define VI_XI_LOOP_WITH_CARRY(BODY) \
-  require(P.VU.vlmul == 1 || insn.rd() != 0); \
+  require(insn.rd() != 0); \
   VI_CHECK_SSS(false); \
   VI_GENERAL_LOOP_BASE \
   VI_MASK_VARS \
diff --git a/riscv/insns/vcompress_vm.h b/riscv/insns/vcompress_vm.h
index a2b810a..325e40a 100644
--- a/riscv/insns/vcompress_vm.h
+++ b/riscv/insns/vcompress_vm.h
@@ -1,9 +1,9 @@
 // vcompress vd, vs2, vs1
 require(P.VU.vstart == 0);
-require((insn.rd() & (P.VU.vlmul - 1)) == 0);
-require((insn.rs2() & (P.VU.vlmul - 1)) == 0);
+require_align(insn.rd(), P.VU.vflmul);
+require_align(insn.rs2(), P.VU.vflmul);
 require(insn.rd() != insn.rs2());
-require(!is_overlapped(insn.rd(), P.VU.vlmul, insn.rs1(), 1));
+require_noover(insn.rd(), P.VU.vflmul, insn.rs1(), 1);
 
 reg_t pos = 0;
 
diff --git a/riscv/insns/vfmv_v_f.h b/riscv/insns/vfmv_v_f.h
index e4cdec4..fb9c788 100644
--- a/riscv/insns/vfmv_v_f.h
+++ b/riscv/insns/vfmv_v_f.h
@@ -1,5 +1,5 @@
 // vfmv_vf vd, vs1
-require((insn.rd() & (P.VU.vlmul - 1)) == 0);
+require_align(insn.rd(), P.VU.vflmul);
 VI_VFP_COMMON
 switch(P.VU.vsew) {
   case e16:
diff --git a/riscv/insns/vid_v.h b/riscv/insns/vid_v.h
index 97a0049..786432f 100644
--- a/riscv/insns/vid_v.h
+++ b/riscv/insns/vid_v.h
@@ -6,9 +6,8 @@ reg_t sew = P.VU.vsew;
 reg_t rd_num = insn.rd();
 reg_t rs1_num = insn.rs1();
 reg_t rs2_num = insn.rs2();
-require((rd_num & (P.VU.vlmul - 1)) == 0);
-if (insn.v_vm() == 0 && P.VU.vlmul >= 2) \
-  require(insn.rd() != 0);
+require_align(rd_num, P.VU.vflmul);
+require_vm;
 
 for (reg_t i = P.VU.vstart ; i < P.VU.vl; ++i) {
   VI_LOOP_ELEMENT_SKIP();
diff --git a/riscv/insns/viota_m.h b/riscv/insns/viota_m.h
index 642a7f9..69c0d20 100644
--- a/riscv/insns/viota_m.h
+++ b/riscv/insns/viota_m.h
@@ -7,10 +7,9 @@ reg_t rd_num = insn.rd();
 reg_t rs1_num = insn.rs1();
 reg_t rs2_num = insn.rs2();
 require(P.VU.vstart == 0);
-require(!is_overlapped(rd_num, P.VU.vlmul, rs2_num, 1));
-if (insn.v_vm() == 0)
-  require(!is_overlapped(rd_num, P.VU.vlmul, 0, 1));
-require((rd_num & (P.VU.vlmul - 1)) == 0);
+require_noover(rd_num, P.VU.vflmul, rs2_num, 1);
+require_vm;
+require_align(rd_num, P.VU.vflmul);
 
 int cnt = 0;
 for (reg_t i = 0; i < vl; ++i) {
diff --git a/riscv/insns/vmsbf_m.h b/riscv/insns/vmsbf_m.h
index 14aa2f5..2be6f41 100644
--- a/riscv/insns/vmsbf_m.h
+++ b/riscv/insns/vmsbf_m.h
@@ -2,10 +2,11 @@
 require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
 require_vector;
 require(P.VU.vstart == 0);
+if (insn.v_vm() == 0)
+  require(insn.rd() != 0 && insn.rd() != insn.rs2());
+
 reg_t vl = P.VU.vl;
-reg_t sew = P.VU.vsew;
 reg_t rd_num = insn.rd();
-reg_t rs1_num = insn.rs1();
 reg_t rs2_num = insn.rs2();
 
 bool has_one = false;
diff --git a/riscv/insns/vmsif_m.h b/riscv/insns/vmsif_m.h
index bbdadf3..73aadbc 100644
--- a/riscv/insns/vmsif_m.h
+++ b/riscv/insns/vmsif_m.h
@@ -2,10 +2,11 @@
 require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
 require_vector;
 require(P.VU.vstart == 0);
+if (insn.v_vm() == 0)
+  require(insn.rd() != 0 && insn.rd() != insn.rs2());
+
 reg_t vl = P.VU.vl;
-reg_t sew = P.VU.vsew;
 reg_t rd_num = insn.rd();
-reg_t rs1_num = insn.rs1();
 reg_t rs2_num = insn.rs2();
 
 bool has_one = false;
diff --git a/riscv/insns/vmsof_m.h b/riscv/insns/vmsof_m.h
index 9fa15dd..218ac61 100644
--- a/riscv/insns/vmsof_m.h
+++ b/riscv/insns/vmsof_m.h
@@ -2,10 +2,11 @@
 require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
 require_vector;
 require(P.VU.vstart == 0);
+if (insn.v_vm() == 0)
+  require(insn.rd() != 0 && insn.rd() != insn.rs2());
+
 reg_t vl = P.VU.vl;
-reg_t sew = P.VU.vsew;
 reg_t rd_num = insn.rd();
-reg_t rs1_num = insn.rs1();
 reg_t rs2_num = insn.rs2();
 
 bool has_one = false;
diff --git a/riscv/insns/vmv_s_x.h b/riscv/insns/vmv_s_x.h
index 9964901..74ab9e0 100644
--- a/riscv/insns/vmv_s_x.h
+++ b/riscv/insns/vmv_s_x.h
@@ -1,8 +1,7 @@
 // vmv_s_x: vd[0] = rs1
 require_vector;
 require(insn.v_vm() == 1);
-require(P.VU.vsew == e8 || P.VU.vsew == e16 ||
-        P.VU.vsew == e32 || P.VU.vsew == e64);
+require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
 reg_t vl = P.VU.vl;
 
 if (vl > 0 && P.VU.vstart < vl) {
diff --git a/riscv/insns/vmv_x_s.h b/riscv/insns/vmv_x_s.h
index 086812b..04cad1c 100644
--- a/riscv/insns/vmv_x_s.h
+++ b/riscv/insns/vmv_x_s.h
@@ -1,4 +1,5 @@
 // vmv_x_s: rd = vs2[rs1]
+require_vector;
 require(insn.v_vm() == 1);
 uint64_t xmask = UINT64_MAX >> (64 - P.get_max_xlen());
 reg_t rs1 = RS1;
diff --git a/riscv/insns/vrgather_vi.h b/riscv/insns/vrgather_vi.h
index f63110e..385e9be 100644
--- a/riscv/insns/vrgather_vi.h
+++ b/riscv/insns/vrgather_vi.h
@@ -1,9 +1,8 @@
 // vrgather.vi vd, vs2, zimm5 vm # vd[i] = (zimm5 >= VLMAX) ? 0 : vs2[zimm5];
-require((insn.rd() & (P.VU.vlmul - 1)) == 0);
-require((insn.rs2() & (P.VU.vlmul - 1)) == 0);
+require_align(insn.rd(), P.VU.vflmul);
+require_align(insn.rs2(), P.VU.vflmul);
 require(insn.rd() != insn.rs2());
-if (insn.v_vm() == 0)
-  require(insn.rd() != 0);
+require_vm;
 
 reg_t zimm5 = insn.v_zimm5();
 
diff --git a/riscv/insns/vrgather_vv.h b/riscv/insns/vrgather_vv.h
index 822e197..a3a32f5 100644
--- a/riscv/insns/vrgather_vv.h
+++ b/riscv/insns/vrgather_vv.h
@@ -1,10 +1,9 @@
 // vrgather.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]];
-require((insn.rd() & (P.VU.vlmul - 1)) == 0);
-require((insn.rs2() & (P.VU.vlmul - 1)) == 0);
-require((insn.rs1() & (P.VU.vlmul - 1)) == 0);
+require_align(insn.rd(), P.VU.vflmul);
+require_align(insn.rs2(), P.VU.vflmul);
+require_align(insn.rs1(), P.VU.vflmul);
 require(insn.rd() != insn.rs2() && insn.rd() != insn.rs1());
-if (insn.v_vm() == 0)
-  require(insn.rd() != 0);
+require_vm;
 
 VI_LOOP_BASE
   switch (sew) {
diff --git a/riscv/insns/vrgather_vx.h b/riscv/insns/vrgather_vx.h
index a91d58c..058ffae 100644
--- a/riscv/insns/vrgather_vx.h
+++ b/riscv/insns/vrgather_vx.h
@@ -1,9 +1,8 @@
 // vrgather.vx vd, vs2, rs1, vm # vd[i] = (rs1 >= VLMAX) ? 0 : vs2[rs1];
-require((insn.rd() & (P.VU.vlmul - 1)) == 0);
-require((insn.rs2() & (P.VU.vlmul - 1)) == 0);
+require_align(insn.rd(), P.VU.vflmul);
+require_align(insn.rs2(), P.VU.vflmul);
 require(insn.rd() != insn.rs2());
-if (insn.v_vm() == 0)
-  require(insn.rd() != 0);
+require_vm;
 
 reg_t rs1 = RS1;
 
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 7d0b582..757e7ad 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -373,7 +373,6 @@ reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newT
     new_vlmul = (BITS(newType, 5, 5) << 2) | BITS(newType, 1, 0);
     new_vlmul = (int8_t)(new_vlmul << 5) >> 5;
     vflmul = new_vlmul >= 0 ? 1 << new_vlmul : 1.0 / (1 << -new_vlmul);
-    vlmul = vflmul < 1 ? 1 : vflmul;
     vlmax = (VLEN/vsew) * vflmul;
     vemul = vflmul;
     veew = vsew;
diff --git a/riscv/processor.h b/riscv/processor.h
index 7d2e372..cde1100 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -456,7 +456,7 @@ public:
       reg_t vlmax;
       reg_t vstart, vxrm, vxsat, vl, vtype, vlenb;
       reg_t vma, vta;
-      reg_t vediv, vsew, vlmul;
+      reg_t vediv, vsew;
       reg_t veew;
       float vemul;
       float vflmul;