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| author | YenHaoChen <39526191+YenHaoChen@users.noreply.github.com> | 2023-12-06 15:18:44 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-12-06 15:18:44 +0800 |
| commit | aa0bbeb296417a8e0e0857aeeaca6c545d2e142d (patch) | |
| tree | fb44322ee92762ea1c7dad9f1ea4e95ef7eccce9 | |
| parent | e46586e2b5744c631e4fefede8df9f0108f06b8d (diff) | |
| download | riscv-isa-sim-aa0bbeb296417a8e0e0857aeeaca6c545d2e142d.zip riscv-isa-sim-aa0bbeb296417a8e0e0857aeeaca6c545d2e142d.tar.gz riscv-isa-sim-aa0bbeb296417a8e0e0857aeeaca6c545d2e142d.tar.bz2 | |
miselect: support miselect when enabling smcsrind
Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>
| -rw-r--r-- | riscv/processor.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 0ac6e67..02ff29a 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -543,6 +543,9 @@ void state_t::reset(processor_t* const proc, reg_t max_isa) sscsrind_reg_csr_t::sscsrind_reg_csr_t_p vsireg[6]; if (proc->extension_enabled_const(EXT_SMCSRIND)) { + miselect = std::make_shared<basic_csr_t>(proc, CSR_MISELECT, 0); + csrmap[CSR_MISELECT] = miselect; + const reg_t mireg_csrs[] = { CSR_MIREG, CSR_MIREG2, CSR_MIREG3, CSR_MIREG4, CSR_MIREG5, CSR_MIREG6 }; auto i = 0; for (auto csr : mireg_csrs) { |