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authorAndrew Waterman <andrew@sifive.com>2023-12-08 15:48:22 -0800
committerAndrew Waterman <andrew@sifive.com>2023-12-08 15:48:22 -0800
commit84f1dbaf8e17e51d7f9165ba4c92fd54f3cf3a0d (patch)
tree21bec3e5637ec9dd293bce1b80425b6794a06499
parent6b2ea346b58293fe6145f4bed8af2a0dcd3a6b94 (diff)
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Add Zimop extension
-rw-r--r--disasm/disasm.cc45
-rw-r--r--disasm/isa_parser.cc2
-rw-r--r--riscv/insns/mop_r_N.h2
-rw-r--r--riscv/insns/mop_rr_N.h2
-rw-r--r--riscv/isa_parser.h1
-rw-r--r--riscv/riscv.mk.in5
6 files changed, 56 insertions, 1 deletions
diff --git a/disasm/disasm.cc b/disasm/disasm.cc
index 2e1eab0..08571a2 100644
--- a/disasm/disasm.cc
+++ b/disasm/disasm.cc
@@ -2172,6 +2172,49 @@ void disassembler_t::add_instructions(const isa_parser_t* isa)
DEFINE_RTYPE(czero_nez);
}
+ if (isa->extension_enabled(EXT_ZIMOP)) {
+ DEFINE_R1TYPE(mop_r_0);
+ DEFINE_R1TYPE(mop_r_1);
+ DEFINE_R1TYPE(mop_r_2);
+ DEFINE_R1TYPE(mop_r_3);
+ DEFINE_R1TYPE(mop_r_4);
+ DEFINE_R1TYPE(mop_r_5);
+ DEFINE_R1TYPE(mop_r_6);
+ DEFINE_R1TYPE(mop_r_7);
+ DEFINE_R1TYPE(mop_r_8);
+ DEFINE_R1TYPE(mop_r_9);
+ DEFINE_R1TYPE(mop_r_10);
+ DEFINE_R1TYPE(mop_r_11);
+ DEFINE_R1TYPE(mop_r_12);
+ DEFINE_R1TYPE(mop_r_13);
+ DEFINE_R1TYPE(mop_r_14);
+ DEFINE_R1TYPE(mop_r_15);
+ DEFINE_R1TYPE(mop_r_16);
+ DEFINE_R1TYPE(mop_r_17);
+ DEFINE_R1TYPE(mop_r_18);
+ DEFINE_R1TYPE(mop_r_19);
+ DEFINE_R1TYPE(mop_r_20);
+ DEFINE_R1TYPE(mop_r_21);
+ DEFINE_R1TYPE(mop_r_22);
+ DEFINE_R1TYPE(mop_r_23);
+ DEFINE_R1TYPE(mop_r_24);
+ DEFINE_R1TYPE(mop_r_25);
+ DEFINE_R1TYPE(mop_r_26);
+ DEFINE_R1TYPE(mop_r_27);
+ DEFINE_R1TYPE(mop_r_28);
+ DEFINE_R1TYPE(mop_r_29);
+ DEFINE_R1TYPE(mop_r_30);
+ DEFINE_R1TYPE(mop_r_31);
+ DEFINE_RTYPE(mop_rr_0);
+ DEFINE_RTYPE(mop_rr_1);
+ DEFINE_RTYPE(mop_rr_2);
+ DEFINE_RTYPE(mop_rr_3);
+ DEFINE_RTYPE(mop_rr_4);
+ DEFINE_RTYPE(mop_rr_5);
+ DEFINE_RTYPE(mop_rr_6);
+ DEFINE_RTYPE(mop_rr_7);
+ }
+
if (isa->extension_enabled(EXT_ZCMOP)) {
DISASM_INSN("c.mop.1", c_mop_1, 0, {});
DISASM_INSN("c.mop.3", c_mop_3, 0, {});
@@ -2347,7 +2390,7 @@ disassembler_t::disassembler_t(const isa_parser_t *isa)
// next-highest priority: other instructions in same base ISA
std::string fallback_isa_string = std::string("rv") + std::to_string(isa->get_max_xlen()) +
- "gqchv_zfh_zba_zbb_zbc_zbs_zcb_zicbom_zicboz_zicond_zkn_zkr_zks_svinval_zcmop";
+ "gqchv_zfh_zba_zbb_zbc_zbs_zcb_zicbom_zicboz_zicond_zkn_zkr_zks_svinval_zcmop_zimop";
isa_parser_t fallback_isa(fallback_isa_string.c_str(), DEFAULT_PRIV);
add_instructions(&fallback_isa);
diff --git a/disasm/isa_parser.cc b/disasm/isa_parser.cc
index ef51310..fa8cadd 100644
--- a/disasm/isa_parser.cc
+++ b/disasm/isa_parser.cc
@@ -294,6 +294,8 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv)
extension_table[EXT_SSCSRIND] = true;
} else if (ext_str == "smcntrpmf") {
extension_table[EXT_SMCNTRPMF] = true;
+ } else if (ext_str == "zimop") {
+ extension_table[EXT_ZIMOP] = true;
} else if (ext_str == "zcmop") {
extension_table[EXT_ZCMOP] = true;
} else if (ext_str == "zalasr") {
diff --git a/riscv/insns/mop_r_N.h b/riscv/insns/mop_r_N.h
new file mode 100644
index 0000000..fa2687e
--- /dev/null
+++ b/riscv/insns/mop_r_N.h
@@ -0,0 +1,2 @@
+require_extension(EXT_ZIMOP);
+WRITE_RD(0);
diff --git a/riscv/insns/mop_rr_N.h b/riscv/insns/mop_rr_N.h
new file mode 100644
index 0000000..fa2687e
--- /dev/null
+++ b/riscv/insns/mop_rr_N.h
@@ -0,0 +1,2 @@
+require_extension(EXT_ZIMOP);
+WRITE_RD(0);
diff --git a/riscv/isa_parser.h b/riscv/isa_parser.h
index a84b6fe..7773ba5 100644
--- a/riscv/isa_parser.h
+++ b/riscv/isa_parser.h
@@ -81,6 +81,7 @@ typedef enum {
EXT_SMCSRIND,
EXT_SSCSRIND,
EXT_SMCNTRPMF,
+ EXT_ZIMOP,
EXT_ZCMOP,
EXT_ZALASR,
NUM_ISA_EXTENSIONS
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 76c2ed7..04747c9 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -1388,6 +1388,10 @@ riscv_insn_ext_zvksh = \
vsm3c_vi \
vsm3me_vv \
+riscv_insn_ext_zimop = \
+ mop_r_N \
+ mop_rr_N \
+
riscv_insn_ext_zvk = \
$(riscv_insn_ext_zvbb) \
$(riscv_insn_ext_zvbc) \
@@ -1426,6 +1430,7 @@ riscv_insn_list = \
$(riscv_insn_priv) \
$(riscv_insn_smrnmi) \
$(riscv_insn_svinval) \
+ $(riscv_insn_ext_zimop) \
riscv_gen_srcs = $(addsuffix .cc,$(riscv_insn_list))