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| author | YenHaoChen <howard25336284@gmail.com> | 2023-11-23 17:15:40 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2023-11-24 09:17:57 +0800 |
| commit | 6e6885feed1c1fd31978535aa4ab845006e91efd (patch) | |
| tree | 6483d1cae7f58a68fe4ccb411263dce56dd13698 | |
| parent | 4841ad0238f0b71ca86fb28974765495cc0c34a9 (diff) | |
| download | riscv-isa-sim-6e6885feed1c1fd31978535aa4ab845006e91efd.zip riscv-isa-sim-6e6885feed1c1fd31978535aa4ab845006e91efd.tar.gz riscv-isa-sim-6e6885feed1c1fd31978535aa4ab845006e91efd.tar.bz2 | |
stimecmp: perform menvcfg.STCE permission check when accessing vstimecmp in HS-mode
The spec requires menvcfg.STCE=1 on accessing stimecmp or vstimecmp in a
mode other than M-mode. The previous implementation does not check the
permission on accessing vstimecmp in HS-mode. This commit fixes the
issue by moveing the permission check from virtualized_stimecmp_csr_t to
stimecmp_csr_t, which implements the vstimecmp.
| -rw-r--r-- | riscv/csrs.cc | 8 | ||||
| -rw-r--r-- | riscv/csrs.h | 1 |
2 files changed, 7 insertions, 2 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index e3b5ad4..7bf2d73 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -1535,7 +1535,7 @@ virtualized_stimecmp_csr_t::virtualized_stimecmp_csr_t(processor_t* const proc, virtualized_csr_t(proc, orig, virt) { } -void virtualized_stimecmp_csr_t::verify_permissions(insn_t insn, bool write) const { +void stimecmp_csr_t::verify_permissions(insn_t insn, bool write) const { if (!(state->menvcfg->read() & MENVCFG_STCE)) { // access to (v)stimecmp with MENVCFG.STCE = 0 if (state->prv < PRV_M) @@ -1549,7 +1549,11 @@ void virtualized_stimecmp_csr_t::verify_permissions(insn_t insn, bool write) con throw trap_virtual_instruction(insn.bits()); } - virtualized_csr_t::verify_permissions(insn, write); + basic_csr_t::verify_permissions(insn, write); +} + +void virtualized_stimecmp_csr_t::verify_permissions(insn_t insn, bool write) const { + orig_csr->verify_permissions(insn, write); } scountovf_csr_t::scountovf_csr_t(processor_t* const proc, const reg_t addr): diff --git a/riscv/csrs.h b/riscv/csrs.h index efa7f10..887749a 100644 --- a/riscv/csrs.h +++ b/riscv/csrs.h @@ -780,6 +780,7 @@ class senvcfg_csr_t final: public envcfg_csr_t { class stimecmp_csr_t: public basic_csr_t { public: stimecmp_csr_t(processor_t* const proc, const reg_t addr, const reg_t imask); + virtual void verify_permissions(insn_t insn, bool write) const override; protected: virtual bool unlogged_write(const reg_t val) noexcept override; private: |