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| author | Jerry Zhao <jerryz123@berkeley.edu> | 2023-12-11 15:57:13 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-12-11 15:57:13 -0800 |
| commit | 4d8651be943ea706eb8dcb3443add2e7ccc117a6 (patch) | |
| tree | c88d36f1afbc3c47fb35cbbc6bbc44065ce48716 | |
| parent | f9cd7ee5cf1a05318cdd9545b4dd0d9e4d541e66 (diff) | |
| parent | f1c000837c6251e716463e6d70ef7e959fa2bfed (diff) | |
| download | riscv-isa-sim-4d8651be943ea706eb8dcb3443add2e7ccc117a6.zip riscv-isa-sim-4d8651be943ea706eb8dcb3443add2e7ccc117a6.tar.gz riscv-isa-sim-4d8651be943ea706eb8dcb3443add2e7ccc117a6.tar.bz2 | |
Merge pull request #1313 from endeneer/fdt-parse-clint-sifive
riscv: sim.cc: Parse for "sifive,clint0" if "riscv,clint0" is absent
| -rw-r--r-- | riscv/clint.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/clint.cc b/riscv/clint.cc index 7e7e89c..4423467 100644 --- a/riscv/clint.cc +++ b/riscv/clint.cc @@ -118,7 +118,7 @@ void clint_t::tick(reg_t rtc_ticks) clint_t* clint_parse_from_fdt(const void* fdt, const sim_t* sim, reg_t* base, const std::vector<std::string>& sargs) { - if (fdt_parse_clint(fdt, base, "riscv,clint0") == 0) + if (fdt_parse_clint(fdt, base, "riscv,clint0") == 0 || fdt_parse_clint(fdt, base, "sifive,clint0") == 0) return new clint_t(sim, sim->CPU_HZ / sim->INSNS_PER_RTC_TICK, sim->get_cfg().real_time_clint); |