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author | Parshintsev Anatoly <anatoly.parshintsev@syntacore.com> | 2022-12-29 14:04:15 +0300 |
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committer | Parshintsev Anatoly <anatoly.parshintsev@syntacore.com> | 2023-01-09 19:16:44 +0300 |
commit | 1e6869c17e23a47f9cf62a21eecda32027acebd5 (patch) | |
tree | 524bfcc6926974b5ea73089108cdaa7e76d42de9 | |
parent | e402a8353d2c4f358198c3bb3de38d40f60c730b (diff) | |
download | riscv-isa-sim-1e6869c17e23a47f9cf62a21eecda32027acebd5.zip riscv-isa-sim-1e6869c17e23a47f9cf62a21eecda32027acebd5.tar.gz riscv-isa-sim-1e6869c17e23a47f9cf62a21eecda32027acebd5.tar.bz2 |
get_inclusive_end implementation for mem_cfg_t
The method can simplify proper processing of sitiations when
(base + size) overflows 64-bit interger.
-rw-r--r-- | riscv/cfg.h | 4 | ||||
-rw-r--r-- | spike_main/spike.cc | 5 |
2 files changed, 6 insertions, 3 deletions
diff --git a/riscv/cfg.h b/riscv/cfg.h index dba0b37..1fb358f 100644 --- a/riscv/cfg.h +++ b/riscv/cfg.h @@ -49,6 +49,10 @@ public: return size; } + reg_t get_inclusive_end() const { + return base + size - 1; + } + private: reg_t base; reg_t size; diff --git a/spike_main/spike.cc b/spike_main/spike.cc index 8012489..59dbbf3 100644 --- a/spike_main/spike.cc +++ b/spike_main/spike.cc @@ -216,9 +216,8 @@ static std::vector<mem_cfg_t> parse_mem_layout(const char* arg) const unsigned long long max_allowed_pa = (1ull << MAX_PADDR_BITS) - 1ull; assert(max_allowed_pa <= std::numeric_limits<reg_t>::max()); mem_cfg_t mem_region(base, size); - auto last_pa_region = mem_region.get_base() + mem_region.get_size() - 1; - if (last_pa_region > max_allowed_pa) { - int bits_required = 64 - clz(last_pa_region); + if (mem_region.get_inclusive_end() > max_allowed_pa) { + int bits_required = 64 - clz(mem_region.get_inclusive_end()); fprintf(stderr, "Unsupported memory region " "{base = 0x%" PRIX64 ", size = 0x%" PRIX64 "} specified," " which requires %d bits of physical address\n" |