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| author | Jerry Zhao <jerryz123@berkeley.edu> | 2023-12-11 14:24:48 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-12-11 14:24:48 -0800 |
| commit | 19078c178240b2ada47c512b2b2e6fa5440cf248 (patch) | |
| tree | b439577118fbf738c0dc4bc34f41d8479c258cc6 | |
| parent | f1e0be840434f5f2935981c3cfcf770bdafa98a4 (diff) | |
| parent | 874ac597c5002389303eb49a92ac13f08558639a (diff) | |
| download | riscv-isa-sim-19078c178240b2ada47c512b2b2e6fa5440cf248.zip riscv-isa-sim-19078c178240b2ada47c512b2b2e6fa5440cf248.tar.gz riscv-isa-sim-19078c178240b2ada47c512b2b2e6fa5440cf248.tar.bz2 | |
Merge pull request #1506 from riscv-software-src/fix-1505
Don't enforce alignment constraints vwsll.v[xi] rs1 arg
| -rw-r--r-- | riscv/zvk_ext_macros.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/zvk_ext_macros.h b/riscv/zvk_ext_macros.h index 75aa56a..f094629 100644 --- a/riscv/zvk_ext_macros.h +++ b/riscv/zvk_ext_macros.h @@ -750,7 +750,7 @@ // - 'rs1', unsigned, SEW width, by value, constant. #define VI_ZVK_VX_WIDENING_ULOOP(BODY) \ do { \ - VI_CHECK_DSS(true); \ + VI_CHECK_DSS(false); \ VI_LOOP_BASE \ switch (sew) { \ case e8: { \ @@ -788,7 +788,7 @@ // - 'zimm5', unsigned, SEW width, by value, constant. #define VI_ZVK_VI_WIDENING_ULOOP(BODY) \ do { \ - VI_CHECK_DSS(true); \ + VI_CHECK_DSS(false); \ VI_LOOP_BASE \ switch (sew) { \ case e8: { \ |