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| author | Andrew Waterman <andrew@sifive.com> | 2023-11-29 11:55:34 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-11-29 11:55:34 -0800 |
| commit | 0c1397661ce383fa303bd878b2fc1172f3ad9213 (patch) | |
| tree | 74a27266b0c088e4ef75b8ce9f1400a86affa665 | |
| parent | 3bc4f0f8fd8fe5131decb7b6b5a5a3ed77fa179c (diff) | |
| parent | a62b69a8893326912cf696d3135d0d59907a560c (diff) | |
| download | riscv-isa-sim-0c1397661ce383fa303bd878b2fc1172f3ad9213.zip riscv-isa-sim-0c1397661ce383fa303bd878b2fc1172f3ad9213.tar.gz riscv-isa-sim-0c1397661ce383fa303bd878b2fc1172f3ad9213.tar.bz2 | |
Merge pull request #1516 from YenHaoChen/pr-dcsr-ebreakx
fix: dcsr.ebreak(v)[su] hardwired to 0 if unsupport corresponding privilege modes
| -rw-r--r-- | riscv/csrs.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 7bf2d73..4783646 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -1304,10 +1304,10 @@ bool dcsr_csr_t::unlogged_write(const reg_t val) noexcept { step = get_field(val, DCSR_STEP); // TODO: ndreset and fullreset ebreakm = get_field(val, DCSR_EBREAKM); - ebreaks = get_field(val, DCSR_EBREAKS); - ebreaku = get_field(val, DCSR_EBREAKU); - ebreakvs = get_field(val, CSR_DCSR_EBREAKVS); - ebreakvu = get_field(val, CSR_DCSR_EBREAKVU); + ebreaks = proc->extension_enabled('S') ? get_field(val, DCSR_EBREAKS) : false; + ebreaku = proc->extension_enabled('U') ? get_field(val, DCSR_EBREAKU) : false; + ebreakvs = proc->extension_enabled('H') ? get_field(val, CSR_DCSR_EBREAKVS) : false; + ebreakvu = proc->extension_enabled('H') ? get_field(val, CSR_DCSR_EBREAKVU) : false; halt = get_field(val, DCSR_HALT); v = proc->extension_enabled('H') ? get_field(val, CSR_DCSR_V) : false; return true; |