diff options
| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-10-18 19:22:08 -0700 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-10-18 19:22:08 -0700 |
| commit | e638446bd99d5051b1d5a45dd38dab654b153f6a (patch) | |
| tree | 28a909929cdd274a46a3c316659c36cba8a5cbae | |
| parent | 787450f4d9b453ce89c871b3b380706d701c909a (diff) | |
| download | riscv-isa-sim-e638446bd99d5051b1d5a45dd38dab654b153f6a.zip riscv-isa-sim-e638446bd99d5051b1d5a45dd38dab654b153f6a.tar.gz riscv-isa-sim-e638446bd99d5051b1d5a45dd38dab654b153f6a.tar.bz2 | |
clean up SR_EA, the enable accelerator bit in status reg
| -rw-r--r-- | riscv/pcr.h | 4 | ||||
| -rw-r--r-- | riscv/processor.cc | 5 |
2 files changed, 4 insertions, 5 deletions
diff --git a/riscv/pcr.h b/riscv/pcr.h index 75a349f..b90884b 100644 --- a/riscv/pcr.h +++ b/riscv/pcr.h @@ -11,10 +11,10 @@ #define SR_U64 0x00000020 #define SR_S64 0x00000040 #define SR_VM 0x00000080 -#define SR_EV 0x00000100 +#define SR_EA 0x00000100 #define SR_IM 0x00FF0000 #define SR_IP 0xFF000000 -#define SR_ZERO ~(SR_S|SR_PS|SR_EI|SR_PEI|SR_EF|SR_U64|SR_S64|SR_VM|SR_EV|SR_IM|SR_IP) +#define SR_ZERO ~(SR_S|SR_PS|SR_EI|SR_PEI|SR_EF|SR_U64|SR_S64|SR_VM|SR_EA|SR_IM|SR_IP) #define SR_IM_SHIFT 16 #define SR_IP_SHIFT 24 diff --git a/riscv/processor.cc b/riscv/processor.cc index ac5c1f7..3fe0d99 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -210,9 +210,8 @@ reg_t processor_t::set_pcr(int which, reg_t val) #ifndef RISCV_ENABLE_FPU state.sr &= ~SR_EF; #endif -#ifndef RISCV_ENABLE_VEC - state.sr &= ~SR_EV; -#endif + if (!ext) + state.sr &= ~SR_EA; state.sr &= ~SR_ZERO; mmu->flush_tlb(); break; |