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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-08-07 20:13:33 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-08-08 15:05:52 -0700 |
| commit | b0af18ed449fb433ae5fce1cf8eb5e1e25ae9190 (patch) | |
| tree | d2062766ae058c8247216f4766dde1c5a1ae47a5 | |
| parent | 15daa31a545573b0848a5f2b9d4dee2da4050290 (diff) | |
| download | riscv-isa-sim-b0af18ed449fb433ae5fce1cf8eb5e1e25ae9190.zip riscv-isa-sim-b0af18ed449fb433ae5fce1cf8eb5e1e25ae9190.tar.gz riscv-isa-sim-b0af18ed449fb433ae5fce1cf8eb5e1e25ae9190.tar.bz2 | |
Ignore JALR's effective address LSB
| -rw-r--r-- | riscv/insns/jalr.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/jalr.h b/riscv/insns/jalr.h index 91be911..6f17ab1 100644 --- a/riscv/insns/jalr.h +++ b/riscv/insns/jalr.h @@ -1,3 +1,3 @@ reg_t temp = RS1; RD = npc; -set_pc(temp + SIMM); +set_pc((temp + SIMM) & ~1); |