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| author | Scott Beamer <sbeamer@eecs.berkeley.edu> | 2013-09-23 15:49:23 -0700 |
|---|---|---|
| committer | Scott Beamer <sbeamer@eecs.berkeley.edu> | 2013-09-23 15:49:23 -0700 |
| commit | 548315acd9936fb0352281032f414639508560f3 (patch) | |
| tree | ab2114dfd61644ea1db528f5e684a88f900d94d3 | |
| parent | 2deb1197bc57bf732a900671e653073b37d67398 (diff) | |
| download | riscv-isa-sim-548315acd9936fb0352281032f414639508560f3.zip riscv-isa-sim-548315acd9936fb0352281032f414639508560f3.tar.gz riscv-isa-sim-548315acd9936fb0352281032f414639508560f3.tar.bz2 | |
fixes compile bug for not being able to find std::logic_error
| -rw-r--r-- | riscv/processor.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 2bd2155..839c846 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -12,6 +12,7 @@ #include <iostream> #include <assert.h> #include <limits.h> +#include <stdexcept> processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id) : sim(_sim), mmu(_mmu), ext(NULL), id(_id), opcode_bits(0) |