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| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-10-16 14:26:13 -0700 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-10-16 14:26:13 -0700 |
| commit | 196370f186778e149c0002b73249750e530c8dc7 (patch) | |
| tree | ad7d617442289471a01cc18e4b1e8cbf094cfce9 | |
| parent | 2f1f9a4fbc7bc45cf277b6a0d8d7d825efdbbb33 (diff) | |
| download | riscv-isa-sim-196370f186778e149c0002b73249750e530c8dc7.zip riscv-isa-sim-196370f186778e149c0002b73249750e530c8dc7.tar.gz riscv-isa-sim-196370f186778e149c0002b73249750e530c8dc7.tar.bz2 | |
fix missing null check when there's no extension
| -rw-r--r-- | riscv/processor.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 652a170..77a81b3 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -66,7 +66,8 @@ void processor_t::reset(bool value) run = !value; state.reset(); // reset the core - ext->reset(); // reset the extension + if (ext) + ext->reset(); // reset the extension } uint32_t processor_t::set_fsr(uint32_t val) |