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author | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-09-10 02:07:08 -0700 |
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committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-09-10 02:07:08 -0700 |
commit | 01dab8dbd6dbad38da740d963975b71bf524c39f (patch) | |
tree | 227d98935954a88ff2214336a87a754e9232cb01 | |
parent | 0642f4db9295a8f96354cdb27432484904ff4214 (diff) | |
download | riscv-isa-sim-01dab8dbd6dbad38da740d963975b71bf524c39f.zip riscv-isa-sim-01dab8dbd6dbad38da740d963975b71bf524c39f.tar.gz riscv-isa-sim-01dab8dbd6dbad38da740d963975b71bf524c39f.tar.bz2 |
Don't tick HTIF as often
-rw-r--r-- | riscv/sim.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index 9ab61b6..f01e931 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -87,10 +87,6 @@ void sim_t::step(size_t n, bool noisy) { for (size_t i = 0, steps = 0; i < n; i += steps) { - htif->tick(); - if (!running()) - break; - steps = std::min(n - i, INTERLEAVE - current_step); procs[current_proc]->step(steps, noisy); @@ -101,6 +97,10 @@ void sim_t::step(size_t n, bool noisy) procs[current_proc]->yield_load_reservation(); if (++current_proc == procs.size()) current_proc = 0; + + htif->tick(); + if (!running()) + break; } } } |