diff options
author | eopXD <yueh.ting.chen@gmail.com> | 2021-12-09 10:58:23 +0800 |
---|---|---|
committer | eopXD <yueh.ting.chen@gmail.com> | 2021-12-09 18:59:38 +0800 |
commit | 76bc15ad4bd51108d99aa4daa5af72c164559a3f (patch) | |
tree | f25303694cb016f0af2e2cac2ac1b581e3c23dac | |
parent | 95c06fbc24c7745941689dae37f7d94faddfa8f5 (diff) | |
download | riscv-isa-sim-76bc15ad4bd51108d99aa4daa5af72c164559a3f.zip riscv-isa-sim-76bc15ad4bd51108d99aa4daa5af72c164559a3f.tar.gz riscv-isa-sim-76bc15ad4bd51108d99aa4daa5af72c164559a3f.tar.bz2 |
Simplfy vfcvt
-rw-r--r-- | riscv/decode.h | 34 | ||||
-rw-r--r-- | riscv/insns/vfcvt_f_x_v.h | 19 | ||||
-rw-r--r-- | riscv/insns/vfcvt_f_xu_v.h | 19 | ||||
-rw-r--r-- | riscv/insns/vfcvt_rtz_x_f_v.h | 16 | ||||
-rw-r--r-- | riscv/insns/vfcvt_rtz_xu_f_v.h | 16 | ||||
-rw-r--r-- | riscv/insns/vfcvt_x_f_v.h | 16 | ||||
-rw-r--r-- | riscv/insns/vfcvt_xu_f_v.h | 16 |
7 files changed, 70 insertions, 66 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 5f566ce..541b46b 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -2389,6 +2389,40 @@ reg_t index[P.VU.vlmax]; \ set_fp_exceptions; \ VI_VFP_LOOP_END +#define VI_VFP_CVT_INT_TO_FP(BODY16, BODY32, BODY64, sign) \ + VI_CHECK_SDS(false); \ + switch(P.VU.vsew) { \ + case e16: \ + { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(16, 16, sign), {}, BODY16); } \ + break; \ + case e32: \ + { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(32, 32, sign), {}, BODY32); } \ + break; \ + case e64: \ + { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(64, 64, sign), {}, BODY64); } \ + break; \ + default: \ + require(0); \ + break; \ + } + +#define VI_VFP_CVT_FP_TO_INT(BODY16, BODY32, BODY64, sign) \ + VI_CHECK_SDS(false); \ + switch(P.VU.vsew) { \ + case e16: \ + { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(16, 16, sign), {}, BODY16); } \ + break; \ + case e32: \ + { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(32, 32, sign), {}, BODY32); } \ + break; \ + case e64: \ + { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(64, 64, sign), {}, BODY64); } \ + break; \ + default: \ + require(0); \ + break; \ + } + #define VI_VFP_NCVT_FP_TO_FP(BODY8, BODY16, BODY32, \ CHECK8, CHECK16, CHECK32) \ VI_CHECK_SDS(false); \ diff --git a/riscv/insns/vfcvt_f_x_v.h b/riscv/insns/vfcvt_f_x_v.h index c53b0e1..d094c14 100644 --- a/riscv/insns/vfcvt_f_x_v.h +++ b/riscv/insns/vfcvt_f_x_v.h @@ -1,14 +1,7 @@ // vfcvt.f.x.v vd, vd2, vm -VI_VFP_VF_LOOP -({ - auto vs2_i = P.VU.elt<int16_t>(rs2_num, i); - vd = i32_to_f16(vs2_i); -}, -{ - auto vs2_i = P.VU.elt<int32_t>(rs2_num, i); - vd = i32_to_f32(vs2_i); -}, -{ - auto vs2_i = P.VU.elt<int64_t>(rs2_num, i); - vd = i64_to_f64(vs2_i); -}) +VI_VFP_CVT_INT_TO_FP( + { vd = i32_to_f16(vs2); }, // BODY16 + { vd = i32_to_f32(vs2); }, // BODY32 + { vd = i64_to_f64(vs2); }, // BODY64 + int // sign +) diff --git a/riscv/insns/vfcvt_f_xu_v.h b/riscv/insns/vfcvt_f_xu_v.h index bd03768..64dbb1c 100644 --- a/riscv/insns/vfcvt_f_xu_v.h +++ b/riscv/insns/vfcvt_f_xu_v.h @@ -1,14 +1,7 @@ // vfcvt.f.xu.v vd, vd2, vm -VI_VFP_VF_LOOP -({ - auto vs2_u = P.VU.elt<uint16_t>(rs2_num, i); - vd = ui32_to_f16(vs2_u); -}, -{ - auto vs2_u = P.VU.elt<uint32_t>(rs2_num, i); - vd = ui32_to_f32(vs2_u); -}, -{ - auto vs2_u = P.VU.elt<uint64_t>(rs2_num, i); - vd = ui64_to_f64(vs2_u); -}) +VI_VFP_CVT_INT_TO_FP( + { vd = ui32_to_f16(vs2); }, // BODY16 + { vd = ui32_to_f32(vs2); }, // BODY32 + { vd = ui64_to_f64(vs2); }, // BODY64 + uint // sign +) diff --git a/riscv/insns/vfcvt_rtz_x_f_v.h b/riscv/insns/vfcvt_rtz_x_f_v.h index e7241bd..ecdfa22 100644 --- a/riscv/insns/vfcvt_rtz_x_f_v.h +++ b/riscv/insns/vfcvt_rtz_x_f_v.h @@ -1,11 +1,7 @@ // vfcvt.rtz.x.f.v vd, vd2, vm -VI_VFP_VF_LOOP -({ - P.VU.elt<int16_t>(rd_num, i) = f16_to_i16(vs2, softfloat_round_minMag, true); -}, -{ - P.VU.elt<int32_t>(rd_num, i) = f32_to_i32(vs2, softfloat_round_minMag, true); -}, -{ - P.VU.elt<int64_t>(rd_num, i) = f64_to_i64(vs2, softfloat_round_minMag, true); -}) +VI_VFP_CVT_FP_TO_INT( + { vd = f16_to_i16(vs2, softfloat_round_minMag, true); }, // BODY16 + { vd = f32_to_i32(vs2, softfloat_round_minMag, true); }, // BODY32 + { vd = f64_to_i64(vs2, softfloat_round_minMag, true); }, // BODY64 + int // sign +) diff --git a/riscv/insns/vfcvt_rtz_xu_f_v.h b/riscv/insns/vfcvt_rtz_xu_f_v.h index d3d266d..87585d2 100644 --- a/riscv/insns/vfcvt_rtz_xu_f_v.h +++ b/riscv/insns/vfcvt_rtz_xu_f_v.h @@ -1,11 +1,7 @@ // vfcvt.rtz.xu.f.v vd, vd2, vm -VI_VFP_VF_LOOP -({ - P.VU.elt<uint16_t>(rd_num, i) = f16_to_ui16(vs2, softfloat_round_minMag, true); -}, -{ - P.VU.elt<uint32_t>(rd_num, i) = f32_to_ui32(vs2, softfloat_round_minMag, true); -}, -{ - P.VU.elt<uint64_t>(rd_num, i) = f64_to_ui64(vs2, softfloat_round_minMag, true); -}) +VI_VFP_CVT_FP_TO_INT( + { vd = f16_to_ui16(vs2, softfloat_round_minMag, true); }, // BODY16 + { vd = f32_to_ui32(vs2, softfloat_round_minMag, true); }, // BODY32 + { vd = f64_to_ui64(vs2, softfloat_round_minMag, true); }, // BODY64 + uint // sign +) diff --git a/riscv/insns/vfcvt_x_f_v.h b/riscv/insns/vfcvt_x_f_v.h index 7e507a3..4f21b52 100644 --- a/riscv/insns/vfcvt_x_f_v.h +++ b/riscv/insns/vfcvt_x_f_v.h @@ -1,11 +1,7 @@ // vfcvt.x.f.v vd, vd2, vm -VI_VFP_VF_LOOP -({ - P.VU.elt<int16_t>(rd_num, i) = f16_to_i16(vs2, STATE.frm->read(), true); -}, -{ - P.VU.elt<int32_t>(rd_num, i) = f32_to_i32(vs2, STATE.frm->read(), true); -}, -{ - P.VU.elt<int64_t>(rd_num, i) = f64_to_i64(vs2, STATE.frm->read(), true); -}) +VI_VFP_CVT_FP_TO_INT( + { vd = f16_to_i16(vs2, softfloat_roundingMode, true); }, // BODY16 + { vd = f32_to_i32(vs2, softfloat_roundingMode, true); }, // BODY32 + { vd = f64_to_i64(vs2, softfloat_roundingMode, true); }, // BODY64 + int // sign +) diff --git a/riscv/insns/vfcvt_xu_f_v.h b/riscv/insns/vfcvt_xu_f_v.h index 51c00ca..ba50fff 100644 --- a/riscv/insns/vfcvt_xu_f_v.h +++ b/riscv/insns/vfcvt_xu_f_v.h @@ -1,11 +1,7 @@ // vfcvt.xu.f.v vd, vd2, vm -VI_VFP_VV_LOOP -({ - P.VU.elt<uint16_t>(rd_num, i) = f16_to_ui16(vs2, STATE.frm->read(), true); -}, -{ - P.VU.elt<uint32_t>(rd_num, i) = f32_to_ui32(vs2, STATE.frm->read(), true); -}, -{ - P.VU.elt<uint64_t>(rd_num, i) = f64_to_ui64(vs2, STATE.frm->read(), true); -}) +VI_VFP_CVT_FP_TO_INT( + { vd = f16_to_ui16(vs2, softfloat_roundingMode, true); }, // BODY16 + { vd = f32_to_ui32(vs2, softfloat_roundingMode, true); }, // BODY32 + { vd = f64_to_ui64(vs2, softfloat_roundingMode, true); }, // BODY64 + uint // sign +) |