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| author | Quan Nguyen <quannguyen@berkeley.edu> | 2013-11-29 20:21:36 -0800 |
|---|---|---|
| committer | Quan Nguyen <quannguyen@berkeley.edu> | 2013-11-29 20:21:36 -0800 |
| commit | 64785705a4de6b49ee5e97169ff151e1d6d4598b (patch) | |
| tree | 43fe386ceda69177741956e5af8f60a974f0c121 | |
| parent | 05f9118e82283a6225534098487fa2011d065fd1 (diff) | |
| download | riscv-isa-sim-64785705a4de6b49ee5e97169ff151e1d6d4598b.zip riscv-isa-sim-64785705a4de6b49ee5e97169ff151e1d6d4598b.tar.gz riscv-isa-sim-64785705a4de6b49ee5e97169ff151e1d6d4598b.tar.bz2 | |
Remove debug printf in vsetprecconfprec
| -rw-r--r-- | hwacha/insns/vsetprec.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/hwacha/insns/vsetprec.h b/hwacha/insns/vsetprec.h index b36f27c..1588de6 100644 --- a/hwacha/insns/vsetprec.h +++ b/hwacha/insns/vsetprec.h @@ -3,7 +3,6 @@ switch (prec) { case 16: case 32: case 64: - printf("Precision set to %d bits\n", prec); WRITE_PREC(prec); break; |