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author | Andrew Waterman <waterman@eecs.berkeley.edu> | 2014-06-13 02:42:54 -0700 |
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committer | Andrew Waterman <waterman@eecs.berkeley.edu> | 2014-06-13 02:42:54 -0700 |
commit | 1c3a5b1d1b1350f19907d4957467441263ebba0e (patch) | |
tree | b0a115485461707200c9875b554d770dcca48a6a | |
parent | 013657ac8c0ac0c4c2582d3073f1ef180f1c5a02 (diff) | |
download | riscv-isa-sim-1c3a5b1d1b1350f19907d4957467441263ebba0e.zip riscv-isa-sim-1c3a5b1d1b1350f19907d4957467441263ebba0e.tar.gz riscv-isa-sim-1c3a5b1d1b1350f19907d4957467441263ebba0e.tar.bz2 |
Only print commit log if instruction commits
-rw-r--r-- | riscv/decode.h | 4 | ||||
-rw-r--r-- | riscv/processor.cc | 12 | ||||
-rw-r--r-- | riscv/processor.h | 10 |
3 files changed, 21 insertions, 5 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index ceaf492..4c3d274 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -104,7 +104,7 @@ private: bool in_spvr = p->get_state()->sr & SR_S; \ reg_t wdata = value; /* value is a func with side-effects */ \ if (!in_spvr) \ - fprintf(stderr, "x%u 0x%016" PRIx64, insn.rd(), ((uint64_t) wdata)); \ + p->get_state()->log_reg_write = (commit_log_reg_t){insn.rd() << 1, wdata}; \ p->get_state()->XPR.write(insn.rd(), wdata); \ }) #endif @@ -120,7 +120,7 @@ private: bool in_spvr = p->get_state()->sr & SR_S; \ freg_t wdata = value; /* value is a func with side-effects */ \ if (!in_spvr) \ - fprintf(stderr, "f%u 0x%016" PRIx64, insn.rd(), ((uint64_t) wdata)); \ + p->get_state()->log_reg_write = (commit_log_reg_t){(insn.rd() << 1) | 1, wdata}; \ p->get_state()->FPR.write(insn.rd(), wdata); \ }) #endif diff --git a/riscv/processor.cc b/riscv/processor.cc index 8cece3e..e40e65b 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -99,8 +99,13 @@ void processor_t::take_interrupt() static void commit_log(state_t* state, insn_t insn) { #ifdef RISCV_ENABLE_COMMITLOG - if (!(state->sr & SR_S)) + if (!(state->sr & SR_S)) { fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") ", state->pc, insn.bits()); + if (state->log_reg_write.addr) + fprintf(stderr, "%c%02u 0x%016" PRIx64, state->log_reg_write.addr & 1 ? 'f' : 'x', + state->log_reg_write.addr >> 1, state->log_reg_write.data); + state->log_reg_write.addr = 0; + } #endif } @@ -136,9 +141,10 @@ void processor_t::step(size_t n) #define ICACHE_ACCESS(idx) { \ insn_t insn = ic_entry->data.insn.insn; \ insn_func_t func = ic_entry->data.func; \ - commit_log(&state, insn); \ ic_entry++; \ - state.pc = func(this, insn, state.pc); \ + reg_t pc = func(this, insn, state.pc); \ + commit_log(&state, insn); \ + state.pc = pc; \ if (idx < ICACHE_SIZE-1 && unlikely(ic_entry->tag != state.pc)) break; \ } diff --git a/riscv/processor.h b/riscv/processor.h index e2847fa..41268f9 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -23,6 +23,12 @@ struct insn_desc_t insn_func_t rv64; }; +struct commit_log_reg_t +{ + uint32_t addr; + reg_t data; +}; + // architectural state of a RISC-V hart struct state_t { @@ -49,6 +55,10 @@ struct state_t uint32_t frm; reg_t load_reservation; + +#ifdef RISCV_ENABLE_COMMITLOG + commit_log_reg_t log_reg_write; +#endif }; // this class represents one processor in a RISC-V machine. |