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author | Tim Newsome <tim@sifive.com> | 2022-04-22 10:40:01 -0700 |
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committer | Tim Newsome <tim@sifive.com> | 2022-04-22 10:40:01 -0700 |
commit | d9131e3b1dc571a657f9615903d1b7220c7c7d7f (patch) | |
tree | 3af6192b7f9fa3557c4ffad4e760789c2b2b27ac | |
parent | 8e6cf2916b9cb809744ac8dbcc04d2a2b108c5b5 (diff) | |
download | riscv-isa-sim-d9131e3b1dc571a657f9615903d1b7220c7c7d7f.zip riscv-isa-sim-d9131e3b1dc571a657f9615903d1b7220c7c7d7f.tar.gz riscv-isa-sim-d9131e3b1dc571a657f9615903d1b7220c7c7d7f.tar.bz2 |
Remove mcontrol_t.type.
It's not writable anyway.
-rw-r--r-- | riscv/triggers.cc | 4 | ||||
-rw-r--r-- | riscv/triggers.h | 1 |
2 files changed, 2 insertions, 3 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 69888bf..1bcda2a 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -4,7 +4,7 @@ namespace triggers { mcontrol_t::mcontrol_t() : - type(2), maskmax(0), select(false), timing(false), chain_bit(false), + maskmax(0), select(false), timing(false), chain_bit(false), match(MATCH_EQUAL), m(false), h(false), s(false), u(false), execute_bit(false), store_bit(false), load_bit(false) { @@ -13,7 +13,7 @@ mcontrol_t::mcontrol_t() : reg_t mcontrol_t::tdata1_read(const processor_t * const proc) const noexcept { reg_t v = 0; auto xlen = proc->get_xlen(); - v = set_field(v, MCONTROL_TYPE(xlen), type); + v = set_field(v, MCONTROL_TYPE(xlen), 2); v = set_field(v, MCONTROL_DMODE(xlen), dmode); v = set_field(v, MCONTROL_MASKMAX(xlen), maskmax); v = set_field(v, MCONTROL_SELECT, select); diff --git a/riscv/triggers.h b/riscv/triggers.h index 3a9c34b..c21b638 100644 --- a/riscv/triggers.h +++ b/riscv/triggers.h @@ -96,7 +96,6 @@ private: bool simple_match(unsigned xlen, reg_t value) const; public: - uint8_t type; uint8_t maskmax; bool select; bool timing; |