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| author | Shaked Flur <fshaked@gmail.com> | 2022-05-04 19:43:38 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-05-04 11:43:38 -0700 |
| commit | a8245e92fb80023cead1a9c6efb00ff98deb5a09 (patch) | |
| tree | 4f5ff568a05d623b40d13be19fc1d037266bb1bc | |
| parent | 8f46a28436f8874a23c721fc336bbd0285642643 (diff) | |
| download | riscv-isa-sim-a8245e92fb80023cead1a9c6efb00ff98deb5a09.zip riscv-isa-sim-a8245e92fb80023cead1a9c6efb00ff98deb5a09.tar.gz riscv-isa-sim-a8245e92fb80023cead1a9c6efb00ff98deb5a09.tar.bz2 | |
Fix the padding of register names in the log (#987)
This fix print x5 as "x5 ", instead of "x 5".
| -rw-r--r-- | riscv/execute.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index 98e3cdb..a6ea7a4 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -133,7 +133,7 @@ static void commit_log_print_insn(processor_t *p, reg_t pc, insn_t insn) if (prefix == 'c') fprintf(log_file, " c%d_%s ", rd, csr_name(rd)); else - fprintf(log_file, " %c%2d ", prefix, rd); + fprintf(log_file, " %c%-2d ", prefix, rd); if (is_vreg) commit_log_print_value(log_file, size, &p->VU.elt<uint8_t>(rd, 0)); else |