diff options
author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-04-13 15:22:41 +0800 |
---|---|---|
committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-04-14 09:40:17 +0800 |
commit | 750f008e723bb3b20cec41a47ed5cec549447665 (patch) | |
tree | b2f2bc14c74ea90073803517579465c7c7f368a2 | |
parent | c3c04a8be2c641de2b198b90df6c1538eb204120 (diff) | |
download | riscv-isa-sim-750f008e723bb3b20cec41a47ed5cec549447665.zip riscv-isa-sim-750f008e723bb3b20cec41a47ed5cec549447665.tar.gz riscv-isa-sim-750f008e723bb3b20cec41a47ed5cec549447665.tar.bz2 |
add support for overlap instructions
* add DECLARE_OVERLAP_INSN to bind instructions with extension
* add overlap_list.h to contain the declare of all overlapping instructions
* make func function for overlapping instruction return NULL when the coresponding
extension(s) is not supported.
-rw-r--r-- | customext/cflush.cc | 6 | ||||
-rw-r--r-- | riscv/overlap_list.h | 8 | ||||
-rw-r--r-- | riscv/processor.cc | 9 | ||||
-rw-r--r-- | riscv/processor.h | 6 | ||||
-rw-r--r-- | riscv/rocc.cc | 8 |
5 files changed, 28 insertions, 9 deletions
diff --git a/customext/cflush.cc b/customext/cflush.cc index 8b72a97..1a5cfa2 100644 --- a/customext/cflush.cc +++ b/customext/cflush.cc @@ -24,9 +24,9 @@ class cflush_t : public extension_t std::vector<insn_desc_t> get_instructions() { std::vector<insn_desc_t> insns; - insns.push_back((insn_desc_t){0xFC000073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush}); - insns.push_back((insn_desc_t){0xFC200073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush}); - insns.push_back((insn_desc_t){0xFC100073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush}); + insns.push_back((insn_desc_t){true, 0xFC000073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush}); + insns.push_back((insn_desc_t){true, 0xFC200073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush}); + insns.push_back((insn_desc_t){true, 0xFC100073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush}); return insns; } diff --git a/riscv/overlap_list.h b/riscv/overlap_list.h new file mode 100644 index 0000000..2bc7f42 --- /dev/null +++ b/riscv/overlap_list.h @@ -0,0 +1,8 @@ +DECLARE_OVERLAP_INSN(c_fsdsp, 'C') +DECLARE_OVERLAP_INSN(c_fsdsp, 'D') +DECLARE_OVERLAP_INSN(c_fld, 'C') +DECLARE_OVERLAP_INSN(c_fld, 'D') +DECLARE_OVERLAP_INSN(c_fldsp, 'C') +DECLARE_OVERLAP_INSN(c_fldsp, 'D') +DECLARE_OVERLAP_INSN(c_fsd, 'C') +DECLARE_OVERLAP_INSN(c_fsd, 'D') diff --git a/riscv/processor.cc b/riscv/processor.cc index f2b0ab3..ad9944e 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -942,16 +942,23 @@ void processor_t::register_extension(extension_t* x) void processor_t::register_base_instructions() { #define DECLARE_INSN(name, match, mask) \ - insn_bits_t name##_match = (match), name##_mask = (mask); + insn_bits_t name##_match = (match), name##_mask = (mask); \ + bool name##_supported = true; + #include "encoding.h" #undef DECLARE_INSN + #define DECLARE_OVERLAP_INSN(name, ext) { name##_supported &= isa->extension_enabled(ext); } + #include "overlap_list.h" + #undef DECLARE_OVERLAP_INSN + #define DEFINE_INSN(name) \ extern reg_t rv32i_##name(processor_t*, insn_t, reg_t); \ extern reg_t rv64i_##name(processor_t*, insn_t, reg_t); \ extern reg_t rv32e_##name(processor_t*, insn_t, reg_t); \ extern reg_t rv64e_##name(processor_t*, insn_t, reg_t); \ register_insn((insn_desc_t) { \ + name##_supported, \ name##_match, \ name##_mask, \ rv32i_##name, \ diff --git a/riscv/processor.h b/riscv/processor.h index 98ff399..8797ab1 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -29,6 +29,7 @@ reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc); struct insn_desc_t { + bool supported; insn_bits_t match; insn_bits_t mask; insn_func_t rv32i; @@ -38,6 +39,9 @@ struct insn_desc_t insn_func_t func(int xlen, bool rve) { + if (!supported) + return NULL; + if (rve) return xlen == 64 ? rv64e : rv32e; else @@ -46,7 +50,7 @@ struct insn_desc_t static insn_desc_t illegal() { - return {0, 0, &illegal_instruction, &illegal_instruction, &illegal_instruction, &illegal_instruction}; + return {true, 0, 0, &illegal_instruction, &illegal_instruction, &illegal_instruction, &illegal_instruction}; } }; diff --git a/riscv/rocc.cc b/riscv/rocc.cc index f50934f..2d09095 100644 --- a/riscv/rocc.cc +++ b/riscv/rocc.cc @@ -32,10 +32,10 @@ customX(3) std::vector<insn_desc_t> rocc_t::get_instructions() { std::vector<insn_desc_t> insns; - insns.push_back((insn_desc_t){0x0b, 0x7f, &::illegal_instruction, c0, &::illegal_instruction, c0}); - insns.push_back((insn_desc_t){0x2b, 0x7f, &::illegal_instruction, c1, &::illegal_instruction, c1}); - insns.push_back((insn_desc_t){0x5b, 0x7f, &::illegal_instruction, c2, &::illegal_instruction, c2}); - insns.push_back((insn_desc_t){0x7b, 0x7f, &::illegal_instruction, c3, &::illegal_instruction, c3}); + insns.push_back((insn_desc_t){true, 0x0b, 0x7f, &::illegal_instruction, c0, &::illegal_instruction, c0}); + insns.push_back((insn_desc_t){true, 0x2b, 0x7f, &::illegal_instruction, c1, &::illegal_instruction, c1}); + insns.push_back((insn_desc_t){true, 0x5b, 0x7f, &::illegal_instruction, c2, &::illegal_instruction, c2}); + insns.push_back((insn_desc_t){true, 0x7b, 0x7f, &::illegal_instruction, c3, &::illegal_instruction, c3}); return insns; } |