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author | soberl <soberl@nvidia.com> | 2022-05-05 09:43:29 +0800 |
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committer | GitHub <noreply@github.com> | 2022-05-05 09:43:29 +0800 |
commit | 6d2549d2ad54aa3bbe183ca091490422047acdca (patch) | |
tree | fc38ea5ff68d1387d2944073e3693ba4520c87e9 | |
parent | b0fdd88d26ef4b20023e1d2a79cfcb1e9df047de (diff) | |
download | riscv-isa-sim-6d2549d2ad54aa3bbe183ca091490422047acdca.zip riscv-isa-sim-6d2549d2ad54aa3bbe183ca091490422047acdca.tar.gz riscv-isa-sim-6d2549d2ad54aa3bbe183ca091490422047acdca.tar.bz2 |
Append smepmp extension 1.0 to the feature list
-rw-r--r-- | README.md | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -35,6 +35,7 @@ Spike supports the following RISC-V ISA features: - Svinval extension, v1.0 - CMO extension, v1.0 - Debug v0.14 + - Smepmp extension v1.0 As a Spike extension, the remainder of the proposed [Bit-Manipulation Extensions](https://github.com/riscv/riscv-bitmanip) |