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| author | Anup Patel <anup@brainfault.org> | 2022-04-11 10:06:28 +0530 |
|---|---|---|
| committer | Scott Johnson <scott.johnson@arilinc.com> | 2022-04-11 09:23:35 -0700 |
| commit | 4df0c94473e045f288990318c2b512ad7e3bef20 (patch) | |
| tree | d4b39f5061bde127d32a63201476b55dc141858d | |
| parent | 0f15aa09005a12521c27005515e088cbd1b81629 (diff) | |
| download | riscv-isa-sim-4df0c94473e045f288990318c2b512ad7e3bef20.zip riscv-isa-sim-4df0c94473e045f288990318c2b512ad7e3bef20.tar.gz riscv-isa-sim-4df0c94473e045f288990318c2b512ad7e3bef20.tar.bz2 | |
Fix hgatp CSR write
The write mask is incorrectly computed by hgatp_csr_t::unlogged_write()
which leads to hgatp.PPN bits not getting updated upon hgatp CSR write.
This patch fixes hgatp CSR writes and gets KVM RISC-V working again
on Spike.
Fixes: 70b7e9ca2d04 ("mmu: support asid/vmid (#928)")
Signed-off-by: Anup Patel <anup@brainfault.org>
| -rw-r--r-- | riscv/csrs.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 3aaeead..19ebd6a 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -978,7 +978,7 @@ bool hgatp_csr_t::unlogged_write(const reg_t val) noexcept { proc->supports_impl(IMPL_MMU_VMID) ? HGATP32_VMID : 0; } else { mask = (HGATP64_PPN & ((reg_t(1) << (MAX_PADDR_BITS - PGSHIFT)) - 1)) | - proc->supports_impl(IMPL_MMU_VMID) ? HGATP64_VMID : 0; + (proc->supports_impl(IMPL_MMU_VMID) ? HGATP64_VMID : 0); if (get_field(val, HGATP64_MODE) == HGATP_MODE_OFF || (proc->supports_impl(IMPL_MMU_SV39) && get_field(val, HGATP64_MODE) == HGATP_MODE_SV39X4) || |