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author | Tim Newsome <tim@sifive.com> | 2022-03-30 10:22:01 -0700 |
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committer | Tim Newsome <tim@sifive.com> | 2022-04-05 10:33:31 -0700 |
commit | 4216b42785e729968dbcc5f4adc8436a7ffc425a (patch) | |
tree | 6553879fa49f3c745c73aca3a3211dddf3b923cd | |
parent | f381b841ceaf816745604b40b34c951f01d8d6d4 (diff) | |
download | riscv-isa-sim-4216b42785e729968dbcc5f4adc8436a7ffc425a.zip riscv-isa-sim-4216b42785e729968dbcc5f4adc8436a7ffc425a.tar.gz riscv-isa-sim-4216b42785e729968dbcc5f4adc8436a7ffc425a.tar.bz2 |
Make triggers a vector of trigger_t.
Not just mcontrol_t.
-rw-r--r-- | riscv/processor.cc | 2 | ||||
-rw-r--r-- | riscv/processor.h | 2 | ||||
-rw-r--r-- | riscv/triggers.h | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 83f1473..ef2d05b 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -988,7 +988,7 @@ bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes) return false; } -void processor_t::trigger_updated(const std::vector<triggers::mcontrol_t *> *triggers) +void processor_t::trigger_updated(const std::vector<triggers::trigger_t *> *triggers) { mmu->flush_tlb(); mmu->check_triggers_fetch = false; diff --git a/riscv/processor.h b/riscv/processor.h index 0283a99..bd805cc 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -314,7 +314,7 @@ public: HR_GROUP /* Halt requested due to halt group. */ } halt_request; - void trigger_updated(const std::vector<triggers::mcontrol_t *> *triggers); + void trigger_updated(const std::vector<triggers::trigger_t *> *triggers); void set_pmp_num(reg_t pmp_num); void set_pmp_granularity(reg_t pmp_granularity); diff --git a/riscv/triggers.h b/riscv/triggers.h index 53b60d3..e37e455 100644 --- a/riscv/triggers.h +++ b/riscv/triggers.h @@ -127,7 +127,7 @@ public: processor_t *proc; private: - std::vector<mcontrol_t *> triggers; + std::vector<trigger_t *> triggers; }; }; |