aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorAndrew Waterman <andrew@sifive.com>2023-06-17 14:34:32 -0700
committerAndrew Waterman <andrew@sifive.com>2023-06-18 01:23:45 -0700
commit58f9ba084c8943de29caa4503f734a6f752b1068 (patch)
treebcd448e8e91458dc574e064b609e79cd071dfccd
parent69389df41cccc2853709e5a18f7c87693f4b0c3d (diff)
downloadriscv-isa-sim-58f9ba084c8943de29caa4503f734a6f752b1068.zip
riscv-isa-sim-58f9ba084c8943de29caa4503f734a6f752b1068.tar.gz
riscv-isa-sim-58f9ba084c8943de29caa4503f734a6f752b1068.tar.bz2
Remove Xbitmanip from README
-rw-r--r--README.md14
1 files changed, 0 insertions, 14 deletions
diff --git a/README.md b/README.md
index 8d5dc45..e850b6e 100644
--- a/README.md
+++ b/README.md
@@ -53,20 +53,6 @@ Spike supports the following RISC-V ISA features:
- Zvfbfmin extension, v0.6
- Zvfbfwma extension, v0.6
-As a Spike extension, the remainder of the proposed
-[Bit-Manipulation Extensions](https://github.com/riscv/riscv-bitmanip)
-is provided under the Spike-custom extension name _Xbitmanip_.
-These instructions (and, of course, the extension name) are not RISC-V
-standards.
-
-These proposed bit-manipulation extensions can be split into further
-groups: Zbp, Zbs, Zbe, Zbf, Zbc, Zbm, Zbr, Zbt. Note that Zbc is
-ratified, but the original proposal contained some extra instructions
-(64-bit carryless multiplies) which are captured here.
-
-To enable these extensions individually, use the Spike-custom
-extension names _XZbp_, _XZbs_, _XZbc_, and so on.
-
Versioning and APIs
-------------------