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| author | Andrew Waterman <andrew@sifive.com> | 2023-07-26 12:56:21 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-07-26 12:56:21 -0700 |
| commit | ec3c9357ec58bdd2522eef3d7768b9276ab96b0c (patch) | |
| tree | 673d25c8f082c917841ef378cfcf8cc1ea7eb441 | |
| parent | c59e80e980e46b1425016d6a31d7f21c8d9ebfa2 (diff) | |
| parent | 63379810b4d5c469de3ba1a9aeb90a8387df8543 (diff) | |
| download | riscv-isa-sim-ec3c9357ec58bdd2522eef3d7768b9276ab96b0c.zip riscv-isa-sim-ec3c9357ec58bdd2522eef3d7768b9276ab96b0c.tar.gz riscv-isa-sim-ec3c9357ec58bdd2522eef3d7768b9276ab96b0c.tar.bz2 | |
Merge pull request #1427 from YenHaoChen/pr-textra-sbytemask
triggers: fix textra.sbytemask
| -rw-r--r-- | riscv/triggers.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 39a7330..b2b815d 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -84,7 +84,7 @@ bool trigger_t::textra_match(processor_t * const proc) const noexcept assert(CSR_TEXTRA32_SBYTEMASK_LENGTH < CSR_TEXTRA64_SBYTEMASK_LENGTH); for (int i = 0; i < CSR_TEXTRA64_SBYTEMASK_LENGTH; i++) if (sbytemask & (1 << i)) - mask &= 0xff << (i * 8); + mask &= ~(reg_t(0xff) << (i * 8)); if ((state->scontext->read() & mask) != (svalue & mask)) return false; } else if (sselect == SSELECT_ASID) { |