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| author | Atul Khare <atulkhare@rivosinc.com> | 2023-07-10 14:47:54 -0700 |
|---|---|---|
| committer | Atul Khare <atulkhare@rivosinc.com> | 2023-07-19 14:22:51 -0700 |
| commit | a6bc48b95e4c7cbf4e6f70315d884b1fe0a06d7f (patch) | |
| tree | 57792b3c661d79a74ef8be55a44b00f1673375ad | |
| parent | 2d802093471e1c0515e3f58a41da4451afa5103e (diff) | |
| download | riscv-isa-sim-a6bc48b95e4c7cbf4e6f70315d884b1fe0a06d7f.zip riscv-isa-sim-a6bc48b95e4c7cbf4e6f70315d884b1fe0a06d7f.tar.gz riscv-isa-sim-a6bc48b95e4c7cbf4e6f70315d884b1fe0a06d7f.tar.bz2 | |
Rengenerate encoding.h
| -rw-r--r-- | riscv/encoding.h | 32 |
1 files changed, 31 insertions, 1 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index db7b021..9666774 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -4,7 +4,7 @@ /* * This file is auto-generated by running 'make' in - * https://github.com/riscv/riscv-opcodes (3ca60c5) + * https://github.com/riscv/riscv-opcodes (be53d24) */ #ifndef RISCV_CSR_ENCODING_H @@ -3059,6 +3059,11 @@ #define CSR_STIMECMP 0x14d #define CSR_SISELECT 0x150 #define CSR_SIREG 0x151 +#define CSR_SIREG2 0x152 +#define CSR_SIREG3 0x153 +#define CSR_SIREG4 0x155 +#define CSR_SIREG5 0x156 +#define CSR_SIREG6 0x157 #define CSR_STOPEI 0x15c #define CSR_SATP 0x180 #define CSR_SCONTEXT 0x5a8 @@ -3073,6 +3078,11 @@ #define CSR_VSTIMECMP 0x24d #define CSR_VSISELECT 0x250 #define CSR_VSIREG 0x251 +#define CSR_VSIREG2 0x252 +#define CSR_VSIREG3 0x253 +#define CSR_VSIREG4 0x255 +#define CSR_VSIREG5 0x256 +#define CSR_VSIREG6 0x257 #define CSR_VSTOPEI 0x25c #define CSR_VSATP 0x280 #define CSR_HSTATUS 0x600 @@ -3140,6 +3150,11 @@ #define CSR_MTVAL2 0x34b #define CSR_MISELECT 0x350 #define CSR_MIREG 0x351 +#define CSR_MIREG2 0x352 +#define CSR_MIREG3 0x353 +#define CSR_MIREG4 0x355 +#define CSR_MIREG5 0x356 +#define CSR_MIREG6 0x357 #define CSR_MTOPEI 0x35c #define CSR_PMPCFG0 0x3a0 #define CSR_PMPCFG1 0x3a1 @@ -4926,6 +4941,11 @@ DECLARE_CSR(sip, CSR_SIP) DECLARE_CSR(stimecmp, CSR_STIMECMP) DECLARE_CSR(siselect, CSR_SISELECT) DECLARE_CSR(sireg, CSR_SIREG) +DECLARE_CSR(sireg2, CSR_SIREG2) +DECLARE_CSR(sireg3, CSR_SIREG3) +DECLARE_CSR(sireg4, CSR_SIREG4) +DECLARE_CSR(sireg5, CSR_SIREG5) +DECLARE_CSR(sireg6, CSR_SIREG6) DECLARE_CSR(stopei, CSR_STOPEI) DECLARE_CSR(satp, CSR_SATP) DECLARE_CSR(scontext, CSR_SCONTEXT) @@ -4940,6 +4960,11 @@ DECLARE_CSR(vsip, CSR_VSIP) DECLARE_CSR(vstimecmp, CSR_VSTIMECMP) DECLARE_CSR(vsiselect, CSR_VSISELECT) DECLARE_CSR(vsireg, CSR_VSIREG) +DECLARE_CSR(vsireg2, CSR_VSIREG2) +DECLARE_CSR(vsireg3, CSR_VSIREG3) +DECLARE_CSR(vsireg4, CSR_VSIREG4) +DECLARE_CSR(vsireg5, CSR_VSIREG5) +DECLARE_CSR(vsireg6, CSR_VSIREG6) DECLARE_CSR(vstopei, CSR_VSTOPEI) DECLARE_CSR(vsatp, CSR_VSATP) DECLARE_CSR(hstatus, CSR_HSTATUS) @@ -5007,6 +5032,11 @@ DECLARE_CSR(mtinst, CSR_MTINST) DECLARE_CSR(mtval2, CSR_MTVAL2) DECLARE_CSR(miselect, CSR_MISELECT) DECLARE_CSR(mireg, CSR_MIREG) +DECLARE_CSR(mireg2, CSR_MIREG2) +DECLARE_CSR(mireg3, CSR_MIREG3) +DECLARE_CSR(mireg4, CSR_MIREG4) +DECLARE_CSR(mireg5, CSR_MIREG5) +DECLARE_CSR(mireg6, CSR_MIREG6) DECLARE_CSR(mtopei, CSR_MTOPEI) DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) |