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| author | Yinan Xu <xuyinan@ict.ac.cn> | 2023-07-18 10:57:29 +0800 |
|---|---|---|
| committer | Yinan Xu <xuyinan@ict.ac.cn> | 2023-07-18 12:46:57 +0800 |
| commit | 93aad1d355d309ab785e61f66183d96b76dfccc1 (patch) | |
| tree | da75b6e689a0be31e398019c1256a8979deaf07a | |
| parent | e85d2923a5e4fdd7d61cd0cc9f0685c97f451769 (diff) | |
| download | riscv-isa-sim-93aad1d355d309ab785e61f66183d96b76dfccc1.zip riscv-isa-sim-93aad1d355d309ab785e61f66183d96b76dfccc1.tar.gz riscv-isa-sim-93aad1d355d309ab785e61f66183d96b76dfccc1.tar.bz2 | |
mmu: fetch instruction bytes in ascending order
Fetching instruction bytes in descending order would result in
wrong xtval update values.
| -rw-r--r-- | riscv/mmu.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index 46c54ce..8c2bdbe 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -294,13 +294,13 @@ public: } else if (length == 2) { // entire instruction already fetched } else if (length == 6) { - insn |= (insn_bits_t)from_le(*(const uint16_t*)translate_insn_addr_to_host(addr + 4)) << 32; insn |= (insn_bits_t)from_le(*(const uint16_t*)translate_insn_addr_to_host(addr + 2)) << 16; + insn |= (insn_bits_t)from_le(*(const uint16_t*)translate_insn_addr_to_host(addr + 4)) << 32; } else { static_assert(sizeof(insn_bits_t) == 8, "insn_bits_t must be uint64_t"); - insn |= (insn_bits_t)from_le(*(const uint16_t*)translate_insn_addr_to_host(addr + 6)) << 48; - insn |= (insn_bits_t)from_le(*(const uint16_t*)translate_insn_addr_to_host(addr + 4)) << 32; insn |= (insn_bits_t)from_le(*(const uint16_t*)translate_insn_addr_to_host(addr + 2)) << 16; + insn |= (insn_bits_t)from_le(*(const uint16_t*)translate_insn_addr_to_host(addr + 4)) << 32; + insn |= (insn_bits_t)from_le(*(const uint16_t*)translate_insn_addr_to_host(addr + 6)) << 48; } insn_fetch_t fetch = {proc->decode_insn(insn), insn}; |