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| author | YenHaoChen <howard25336284@gmail.com> | 2023-07-19 14:15:57 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2023-07-19 14:16:00 +0800 |
| commit | 8658429647eb6952707e2bf2a3bb4eca75a8e379 (patch) | |
| tree | 9de5ca538d0851eee26b5fccf97c9f6c0d579792 | |
| parent | 4aea5a05ad7bf1b48b2d87e000e6575f68747033 (diff) | |
| download | riscv-isa-sim-8658429647eb6952707e2bf2a3bb4eca75a8e379.zip riscv-isa-sim-8658429647eb6952707e2bf2a3bb4eca75a8e379.tar.gz riscv-isa-sim-8658429647eb6952707e2bf2a3bb4eca75a8e379.tar.bz2 | |
mcontrol/mcontrol6 triggers on cbo.flush/clean
The mcontrol/mcontrol6 store address before has a higher priority over page
faults and access faults. Thus, trigger checking should before the translate().
This commit checks all address of the cache block.
Reference: Debug spec 1.0, 5.5.3 Cache Operations
Reference: CMO spec 1.0.1, 2.5.4 Breakpoint Exceptions and Debug Mode Entry
| -rw-r--r-- | riscv/mmu.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index cfbe57c..a54a483 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -226,6 +226,9 @@ public: } void clean_inval(reg_t addr, bool clean, bool inval) { + auto base = addr & ~(blocksz - 1); + for (size_t offset = 0; offset < blocksz; offset += 1) + check_triggers(triggers::OPERATION_STORE, base + offset, false, addr, std::nullopt); convert_load_traps_to_store_traps({ const reg_t paddr = translate(generate_access_info(addr, LOAD, {false, false, false}), 1); if (sim->reservable(paddr)) { |